| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| unmapped |
|
96.77% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_smoke | 25 | 25 | 100.00 | |||
| dma_memory_smoke | 8.000s | 303.327us | 25 | 25 | 100.00 | |
| dma_handshake_smoke | 25 | 25 | 100.00 | |||
| dma_handshake_smoke | 9.000s | 421.091us | 25 | 25 | 100.00 | |
| dma_generic_smoke | 50 | 50 | 100.00 | |||
| dma_generic_smoke | 9.000s | 7279.788us | 50 | 50 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 91.540us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| dma_csr_rw | 2.000s | 293.604us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| dma_csr_bit_bash | 8.000s | 1887.477us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| dma_csr_aliasing | 5.000s | 268.451us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| dma_csr_mem_rw_with_rand_reset | 2.000s | 161.486us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| dma_csr_rw | 2.000s | 293.604us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 5.000s | 268.451us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_region_lock | 5 | 5 | 100.00 | |||
| dma_memory_region_lock | 121.000s | 21565.078us | 5 | 5 | 100.00 | |
| dma_memory_tl_error | 3 | 3 | 100.00 | |||
| dma_memory_stress | 686.000s | 56339.709us | 3 | 3 | 100.00 | |
| dma_handshake_tl_error | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 601.000s | 479842.362us | 3 | 3 | 100.00 | |
| dma_handshake_stress | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 601.000s | 479842.362us | 3 | 3 | 100.00 | |
| dma_memory_stress | 3 | 3 | 100.00 | |||
| dma_memory_stress | 686.000s | 56339.709us | 3 | 3 | 100.00 | |
| dma_generic_stress | 5 | 5 | 100.00 | |||
| dma_generic_stress | 1256.000s | 343513.806us | 5 | 5 | 100.00 | |
| dma_handshake_mem_buffer_overflow | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 601.000s | 479842.362us | 3 | 3 | 100.00 | |
| dma_abort | 5 | 5 | 100.00 | |||
| dma_abort | 19.000s | 5111.477us | 5 | 5 | 100.00 | |
| dma_stress_all | 3 | 3 | 100.00 | |||
| dma_stress_all | 105.000s | 15685.504us | 3 | 3 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| dma_alert_test | 2.000s | 12.834us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| dma_intr_test | 2.000s | 16.463us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| dma_tl_errors | 5.000s | 170.061us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| dma_tl_errors | 5.000s | 170.061us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 91.540us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 293.604us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 5.000s | 268.451us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 3.000s | 200.182us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 91.540us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 293.604us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 5.000s | 268.451us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 3.000s | 200.182us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_illegal_addr_range | 13 | 13 | 100.00 | |||
| dma_mem_enabled | 31.000s | 234.577us | 5 | 5 | 100.00 | |
| dma_generic_stress | 1256.000s | 343513.806us | 5 | 5 | 100.00 | |
| dma_handshake_stress | 601.000s | 479842.362us | 3 | 3 | 100.00 | |
| dma_config_lock | 15 | 15 | 100.00 | |||
| dma_config_lock | 11.000s | 323.495us | 15 | 15 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| dma_tl_intg_err | 4.000s | 91.743us | 25 | 25 | 100.00 | |
| dma_sec_cm | 2.000s | 80.446us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 30 | 31 | 96.77 | |||
| dma_short_transfer | 216.000s | 192112.485us | 25 | 25 | 100.00 | |
| dma_longer_transfer | 7.000s | 422.493us | 5 | 5 | 100.00 | |
| dma_stress_all_with_rand_reset | 9.000s | 367.179us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| dma_stress_all_with_rand_reset | 95637413226042057690561227779004734589368839276788614346105003682325639181057 | 97 |
UVM_INFO @ 367178562ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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