Simulation Results

Simulation Results: edn/edn0

07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
84.16 %

code
95.28 %

assert
98.45 %

func
58.74 %

block
96.95 %

line
98.68 %

branch
93.23 %

toggle
89.22 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		98.85%
V2S		100.00%
V3		80.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	edn_smoke	2.000s	34.930us	10	10	100.00
csr_hw_reset				1	1	100.00
	edn_csr_hw_reset	2.000s	24.850us	1	1	100.00
csr_rw				5	5	100.00
	edn_csr_rw	2.000s	14.306us	5	5	100.00
csr_bit_bash				1	1	100.00
	edn_csr_bit_bash	5.000s	152.492us	1	1	100.00
csr_aliasing				1	1	100.00
	edn_csr_aliasing	2.000s	47.572us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	edn_csr_mem_rw_with_rand_reset	3.000s	243.484us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	edn_csr_rw	2.000s	14.306us	5	5	100.00
	edn_csr_aliasing	2.000s	47.572us	1	1	100.00

600/607 passed

98.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware				100	100	100.00
	edn_genbits	5.000s	700.985us	100	100	100.00
csrng_commands				100	100	100.00
	edn_genbits	5.000s	700.985us	100	100	100.00
genbits				100	100	100.00
	edn_genbits	5.000s	700.985us	100	100	100.00
interrupts				20	20	100.00
	edn_intr	2.000s	20.378us	20	20	100.00
alerts				200	200	100.00
	edn_alert	3.000s	214.750us	200	200	100.00
errs				100	100	100.00
	edn_err	3.000s	56.106us	100	100	100.00
disable				93	100	93.00
	edn_disable	2.000s	22.858us	50	50	100.00
	edn_disable_auto_req_mode	12.000s	500.000us	43	50	86.00
stress_all				30	30	100.00
	edn_stress_all	9.000s	392.431us	30	30	100.00
intr_test				10	10	100.00
	edn_intr_test	2.000s	150.344us	10	10	100.00
alert_test				10	10	100.00
	edn_alert_test	2.000s	48.359us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	edn_tl_errors	6.000s	159.019us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	edn_tl_errors	6.000s	159.019us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	edn_csr_hw_reset	2.000s	24.850us	1	1	100.00
	edn_csr_rw	2.000s	14.306us	5	5	100.00
	edn_csr_aliasing	2.000s	47.572us	1	1	100.00
	edn_same_csr_outstanding	3.000s	37.730us	5	5	100.00
tl_d_partial_access				12	12	100.00
	edn_csr_hw_reset	2.000s	24.850us	1	1	100.00
	edn_csr_rw	2.000s	14.306us	5	5	100.00
	edn_csr_aliasing	2.000s	47.572us	1	1	100.00
	edn_same_csr_outstanding	3.000s	37.730us	5	5	100.00

V2S

235/235 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	edn_sec_cm	12.000s	3285.620us	5	5	100.00
	edn_tl_intg_err	4.000s	222.492us	25	25	100.00
sec_cm_config_regwen				5	5	100.00
	edn_regwen	2.000s	33.760us	5	5	100.00
sec_cm_config_mubi				200	200	100.00
	edn_alert	3.000s	214.750us	200	200	100.00
sec_cm_main_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	12.000s	3285.620us	5	5	100.00
sec_cm_ack_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	12.000s	3285.620us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	edn_sec_cm	12.000s	3285.620us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	edn_sec_cm	12.000s	3285.620us	5	5	100.00
sec_cm_main_sm_ctr_local_esc				205	205	100.00
	edn_alert	3.000s	214.750us	200	200	100.00
	edn_sec_cm	12.000s	3285.620us	5	5	100.00
sec_cm_cs_rdata_bus_consistency				200	200	100.00
	edn_alert	3.000s	214.750us	200	200	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	edn_tl_intg_err	4.000s	222.492us	25	25	100.00

24/30 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				24	30	80.00
	edn_stress_all_with_rand_reset	94.000s	4886.056us	24	30	80.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				6 test runs
	edn_stress_all_with_rand_reset	65269966985846731954907839939024116547203334618931848990050056731004400832664	179	UVM_INFO @ 1435764575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	12611957314487937502036522192573381807512345040129283783842454964199378879847	184	UVM_INFO @ 1162623204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	14312891872241765722058153813434733811537013162802407876917918240038800678912	290	UVM_INFO @ 3800166720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	17739652568829787690297129206126549262437808578227012153367496656772255593258	170	UVM_INFO @ 1069774419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	61653314607588962970766223008396287011107628242149734903687986992522134269354	232	UVM_INFO @ 1884673963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	28707310012185629224073425938753605823393868676878250824357146369996371785002	166	UVM_INFO @ 744090308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				5 test runs
	edn_disable_auto_req_mode	44406499278563972495260988874334833471579252963427095925596230645883780458859	103	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	62748201387666608075954532465816323106797359264722375819640877659834011969798	103	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	87708269458316018518055793956583225395529143290274410376806575405791161968040	104	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	17196876703332468236906524889497130815838573201119231975017769054976677936230	103	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	47520223328637660313345470273603981058182077386922861523734988724568478553756	103	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.				2 test runs
	edn_disable_auto_req_mode	89806551169693768981771274941660544153498027846277599916942011712699764153703	103	UVM_INFO @ 55147356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	88278384116902707545938163038047351830476548011240419917876426365593098144991	103	UVM_INFO @ 62782349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---