Simulation Results: edn/edn1

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 95.70 %
  • assert
  • 98.70 %
  • func
  • 92.44 %
  • line
  • 98.41 %
  • branch
  • 94.16 %
  • cond
  • 94.31 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
98.85%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.190s 36.241us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 26.587us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.190s 48.974us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.140s 847.783us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.160s 321.079us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.700s 95.123us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.190s 48.974us 5 5 100.00
edn_csr_aliasing 1.160s 321.079us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.350s 335.704us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.350s 335.704us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.350s 335.704us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.260s 25.578us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.720s 432.668us 200 200 100.00
errs 100 100 100.00
edn_err 1.510s 72.067us 100 100 100.00
disable 93 100 93.00
edn_disable 1.210s 13.795us 50 50 100.00
edn_disable_auto_req_mode 12.530s 500.000us 43 50 86.00
stress_all 30 30 100.00
edn_stress_all 7.300s 400.514us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.090s 87.598us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.250s 18.186us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.790s 630.123us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.790s 630.123us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.860s 26.587us 1 1 100.00
edn_csr_rw 1.190s 48.974us 5 5 100.00
edn_csr_aliasing 1.160s 321.079us 1 1 100.00
edn_same_csr_outstanding 1.460s 120.826us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.860s 26.587us 1 1 100.00
edn_csr_rw 1.190s 48.974us 5 5 100.00
edn_csr_aliasing 1.160s 321.079us 1 1 100.00
edn_same_csr_outstanding 1.460s 120.826us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 5.530s 642.242us 5 5 100.00
edn_tl_intg_err 3.910s 1370.363us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.140s 48.621us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.720s 432.668us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.530s 642.242us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.530s 642.242us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.530s 642.242us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.530s 642.242us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.720s 432.668us 200 200 100.00
edn_sec_cm 5.530s 642.242us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.720s 432.668us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.910s 1370.363us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 30 90.00
edn_stress_all_with_rand_reset 89.710s 17433.097us 27 30 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 6 test runs
edn_disable_auto_req_mode 39088668874152137479651073151544035727818045962514286073264614549467207774589 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 2333300726445819788286203484731069649510496412181229732704458365833223012145 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 26694311198464194769341893598620019614591154271337986298147722727584816151587 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 85904367303736371352643204372763440186466956596094910727855284959442984090611 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 88194130047427719695944816111500781993588134771555251309903627249206793245975 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 284062351194526115545793143830754614509329498426248869574740181864692517209 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 46728383843162750842010084059733366988887932158076745628686569220745908527075 157
UVM_INFO @ 998719922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 16481888300661642196700864361699136619695625877330310330895537056304506956856 128
UVM_INFO @ 253551572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 66713349523985034007764979665260059304616909445376389850791277400191142543273 292
UVM_INFO @ 4066966416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_disable_auto_req_mode 57181856119935229655530533699241881087919943390759625427369772251816665721535 89
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 54168099 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup