Simulation Results: hmac

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.77 %
  • code
  • 96.14 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.74 %
  • line
  • 98.44 %
  • branch
  • 94.35 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 19.000s 1480.265us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 150.167us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 15.819us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.000s 2261.421us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 238.706us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 3.000s 31.815us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 15.819us 5 5 100.00
hmac_csr_aliasing 3.000s 238.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 85.000s 10440.399us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 111.000s 2562.414us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 340.000s 25208.155us 30 30 100.00
hmac_test_sha384_vectors 676.000s 21534.819us 75 75 100.00
hmac_test_sha512_vectors 699.000s 20004.073us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 443.923us 50 50 100.00
hmac_test_hmac384_vectors 23.000s 524.813us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 8148.850us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 40.000s 2388.007us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 277.000s 27505.665us 10 10 100.00
error 10 10 100.00
hmac_error 138.000s 10100.615us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 153.000s 12801.272us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 19.000s 1480.265us 10 10 100.00
hmac_long_msg 85.000s 10440.399us 10 10 100.00
hmac_back_pressure 111.000s 2562.414us 25 25 100.00
hmac_datapath_stress 277.000s 27505.665us 10 10 100.00
hmac_burst_wr 40.000s 2388.007us 50 50 100.00
hmac_stress_all 993.000s 25601.899us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 19.000s 1480.265us 10 10 100.00
hmac_long_msg 85.000s 10440.399us 10 10 100.00
hmac_back_pressure 111.000s 2562.414us 25 25 100.00
hmac_datapath_stress 277.000s 27505.665us 10 10 100.00
hmac_wipe_secret 153.000s 12801.272us 10 10 100.00
hmac_test_sha256_vectors 340.000s 25208.155us 30 30 100.00
hmac_test_sha384_vectors 676.000s 21534.819us 75 75 100.00
hmac_test_sha512_vectors 699.000s 20004.073us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 443.923us 50 50 100.00
hmac_test_hmac384_vectors 23.000s 524.813us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 8148.850us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 19.000s 1480.265us 10 10 100.00
hmac_long_msg 85.000s 10440.399us 10 10 100.00
hmac_back_pressure 111.000s 2562.414us 25 25 100.00
hmac_datapath_stress 277.000s 27505.665us 10 10 100.00
hmac_burst_wr 40.000s 2388.007us 50 50 100.00
hmac_error 138.000s 10100.615us 10 10 100.00
hmac_wipe_secret 153.000s 12801.272us 10 10 100.00
hmac_test_sha256_vectors 340.000s 25208.155us 30 30 100.00
hmac_test_sha384_vectors 676.000s 21534.819us 75 75 100.00
hmac_test_sha512_vectors 699.000s 20004.073us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 443.923us 50 50 100.00
hmac_test_hmac384_vectors 23.000s 524.813us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 8148.850us 75 75 100.00
hmac_stress_all 993.000s 25601.899us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 993.000s 25601.899us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 24.294us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 27.359us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 6.000s 611.264us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 6.000s 611.264us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 150.167us 1 1 100.00
hmac_csr_rw 2.000s 15.819us 5 5 100.00
hmac_csr_aliasing 3.000s 238.706us 1 1 100.00
hmac_same_csr_outstanding 3.000s 99.468us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 150.167us 1 1 100.00
hmac_csr_rw 2.000s 15.819us 5 5 100.00
hmac_csr_aliasing 3.000s 238.706us 1 1 100.00
hmac_same_csr_outstanding 3.000s 99.468us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 372.432us 5 5 100.00
hmac_tl_intg_err 5.000s 3242.375us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.000s 3242.375us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 19.000s 1480.265us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 10.000s 654.046us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 315.000s 7118.308us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 53.078us 1 1 100.00