Simulation Results: keymgr_dpe/darjeeling

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 66.30 %
  • code
  • 83.84 %
  • assert
  • 97.18 %
  • func
  • 17.88 %
  • block
  • 97.98 %
  • line
  • 98.66 %
  • branch
  • 93.43 %
  • toggle
  • 61.74 %
  • FSM
  • 81.54 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
keymgr_dpe_smoke 19.000s 12389.528us 10 10 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.000s 33.639us 1 1 100.00
csr_rw 5 5 100.00
keymgr_dpe_csr_rw 2.000s 47.925us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 5.000s 129.062us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 3.000s 1258.788us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.000s 39.133us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_dpe_csr_rw 2.000s 47.925us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 1258.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 10 10 100.00
keymgr_dpe_intr_test 2.000s 89.606us 10 10 100.00
alert_test 10 10 100.00
keymgr_dpe_alert_test 2.000s 29.798us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_dpe_tl_errors 4.000s 141.190us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_dpe_tl_errors 4.000s 141.190us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_dpe_csr_hw_reset 1.000s 33.639us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 47.925us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 1258.788us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 84.705us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_dpe_csr_hw_reset 1.000s 33.639us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 47.925us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 1258.788us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 84.705us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
keymgr_dpe_sec_cm 9.000s 930.689us 5 5 100.00
keymgr_dpe_tl_intg_err 5.000s 777.351us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 511.073us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 511.073us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 511.073us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 511.073us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 6.000s 803.723us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 9.000s 930.689us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 9.000s 930.689us 5 5 100.00