Simulation Results: lc_ctrl/volatile_unlock_disabled

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.91 %
  • code
  • 93.20 %
  • assert
  • 96.83 %
  • func
  • 88.71 %
  • block
  • 96.70 %
  • line
  • 97.39 %
  • branch
  • 91.61 %
  • toggle
  • 88.57 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.59%
V2S
99.33%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.000s 709.012us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 24.000s 17.779us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 16.000s 22.425us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 25.000s 19.500us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 25.000s 44.793us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 23.000s 82.259us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 16.000s 22.425us 5 5 100.00
lc_ctrl_csr_aliasing 25.000s 44.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 172.085us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 4918.691us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 24.000s 35.600us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.000s 387.838us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 7.000s 427.177us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 16.000s 1290.013us 20 20 100.00
security_escalation 135 140 96.43
lc_ctrl_state_failure 7.000s 427.177us 20 20 100.00
lc_ctrl_prog_failure 3.000s 387.838us 20 20 100.00
lc_ctrl_errors 16.000s 1290.013us 20 20 100.00
lc_ctrl_security_escalation 6.000s 2163.900us 20 20 100.00
lc_ctrl_jtag_state_failure 26.000s 7346.171us 15 20 75.00
lc_ctrl_jtag_prog_failure 12.000s 952.690us 20 20 100.00
lc_ctrl_jtag_errors 28.000s 6068.578us 20 20 100.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 7.000s 1326.215us 20 20 100.00
lc_ctrl_jtag_state_post_trans 8.000s 707.560us 19 20 95.00
lc_ctrl_jtag_prog_failure 12.000s 952.690us 20 20 100.00
lc_ctrl_jtag_errors 28.000s 6068.578us 20 20 100.00
lc_ctrl_jtag_access 17.000s 711.313us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 12.000s 3490.065us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 8.000s 215.800us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 282.994us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 13.000s 1293.104us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 13.000s 792.427us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 140.658us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 915.005us 10 10 100.00
lc_ctrl_jtag_alert_test 9.000s 207.568us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 31.000s 3669.486us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 14.322us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 147.000s 62515.055us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 24.000s 120.090us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 235.719us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 235.719us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 24.000s 17.779us 1 1 100.00
lc_ctrl_csr_rw 16.000s 22.425us 5 5 100.00
lc_ctrl_csr_aliasing 25.000s 44.793us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 73.282us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 24.000s 17.779us 1 1 100.00
lc_ctrl_csr_rw 16.000s 22.425us 5 5 100.00
lc_ctrl_csr_aliasing 25.000s 44.793us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 73.282us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 4.000s 871.448us 5 5 100.00
lc_ctrl_tl_intg_err 7.000s 261.344us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 7.000s 261.344us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 4918.691us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 427.177us 20 20 100.00
lc_ctrl_sec_cm 4.000s 871.448us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 427.177us 20 20 100.00
lc_ctrl_sec_cm 4.000s 871.448us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 427.177us 20 20 100.00
lc_ctrl_sec_cm 4.000s 871.448us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 427.177us 20 20 100.00
lc_ctrl_sec_cm 4.000s 871.448us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 427.177us 20 20 100.00
lc_ctrl_sec_cm 4.000s 871.448us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 427.177us 20 20 100.00
lc_ctrl_sec_cm 4.000s 871.448us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 427.177us 20 20 100.00
lc_ctrl_sec_cm 4.000s 871.448us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 7.000s 427.177us 20 20 100.00
lc_ctrl_sec_cm 4.000s 871.448us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 6.000s 2163.900us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 39 40 97.50
lc_ctrl_state_post_trans 4.000s 172.085us 20 20 100.00
lc_ctrl_jtag_state_post_trans 8.000s 707.560us 19 20 95.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.000s 3243.057us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.000s 3243.057us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 8.000s 9201.459us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.000s 561.705us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.000s 561.705us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 10 70.00
lc_ctrl_stress_all_with_rand_reset 43.000s 14782.315us 7 10 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 6 test runs
lc_ctrl_jtag_state_post_trans 78673122140920827102328816623076738361142802472578929574015023078649048965562 175
UVM_INFO @ 108792241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 72990099084091479318247804845726473149841769998970296067615274039722133051559 175
UVM_INFO @ 44859852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 74997131584865611483801878505257244130603501034276049452418723213110960934293 175
UVM_INFO @ 32512622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 114367625318200986024244704660465803366623203847387010522160418839232310602135 175
UVM_INFO @ 85796064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 32466194159154677960446865158934874718852603765300724268691813445187984034677 175
UVM_INFO @ 33300428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 26382070851642543216627102926861170198573635318011492356839526378097169953982 178
UVM_INFO @ 267160257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
lc_ctrl_stress_all_with_rand_reset 104841729968937302633241058776790185237888638217499090750132098297216307512460 261
UVM_INFO @ 2433940775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15048910163769999825887461890251613639386586409108980927328773503017666684194 937
UVM_INFO @ 9518283148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13503815343970122917127180972839181906237626174476148092446631751094955938347 2574
UVM_INFO @ 23534016161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---