Simulation Results: lc_ctrl/volatile_unlock_enabled

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.34 %
  • code
  • 94.17 %
  • assert
  • 96.83 %
  • func
  • 89.03 %
  • block
  • 97.16 %
  • line
  • 97.69 %
  • branch
  • 92.79 %
  • toggle
  • 88.60 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.77%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.000s 1219.419us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 171.893us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 51.982us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 106.057us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 78.690us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 3.000s 56.624us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 51.982us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 78.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 623.590us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 8.000s 282.345us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 13.139us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.000s 97.634us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 7.000s 325.703us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 8.000s 482.667us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 7.000s 325.703us 20 20 100.00
lc_ctrl_prog_failure 3.000s 97.634us 20 20 100.00
lc_ctrl_errors 8.000s 482.667us 20 20 100.00
lc_ctrl_security_escalation 7.000s 379.369us 20 20 100.00
lc_ctrl_jtag_state_failure 27.000s 14111.437us 19 20 95.00
lc_ctrl_jtag_prog_failure 11.000s 531.476us 20 20 100.00
lc_ctrl_jtag_errors 26.000s 19927.294us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 7.000s 887.957us 20 20 100.00
lc_ctrl_jtag_state_post_trans 11.000s 1181.102us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.000s 531.476us 20 20 100.00
lc_ctrl_jtag_errors 26.000s 19927.294us 20 20 100.00
lc_ctrl_jtag_access 9.000s 606.269us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 12.000s 1059.897us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 102.752us 10 10 100.00
lc_ctrl_jtag_csr_rw 7.000s 132.978us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 13.000s 7021.316us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 9.000s 6588.224us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 58.872us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 553.710us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 130.506us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 12.000s 1399.480us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 56.217us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 149.000s 35176.904us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 7.000s 16.224us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 535.414us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 535.414us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 171.893us 1 1 100.00
lc_ctrl_csr_rw 2.000s 51.982us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 78.690us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 18.627us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 171.893us 1 1 100.00
lc_ctrl_csr_rw 2.000s 51.982us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 78.690us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 18.627us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 4.000s 488.264us 5 5 100.00
lc_ctrl_tl_intg_err 3.000s 338.259us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.000s 338.259us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 8.000s 282.345us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 325.703us 20 20 100.00
lc_ctrl_sec_cm 4.000s 488.264us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 325.703us 20 20 100.00
lc_ctrl_sec_cm 4.000s 488.264us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 325.703us 20 20 100.00
lc_ctrl_sec_cm 4.000s 488.264us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 325.703us 20 20 100.00
lc_ctrl_sec_cm 4.000s 488.264us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 325.703us 20 20 100.00
lc_ctrl_sec_cm 4.000s 488.264us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 325.703us 20 20 100.00
lc_ctrl_sec_cm 4.000s 488.264us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 325.703us 20 20 100.00
lc_ctrl_sec_cm 4.000s 488.264us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 7.000s 325.703us 20 20 100.00
lc_ctrl_sec_cm 4.000s 488.264us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 7.000s 379.369us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 4.000s 623.590us 20 20 100.00
lc_ctrl_jtag_state_post_trans 11.000s 1181.102us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 8.000s 2068.766us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 8.000s 2068.766us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 8.000s 6262.446us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.000s 2333.299us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.000s 2333.299us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 60.000s 24875.007us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 90369089409296348322572560756291204710221644517590845364457524129300766479220 1824
UVM_INFO @ 7632221762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22913558555205339861457935781520556292568478253717440327295280539739438275659 211
UVM_INFO @ 1020257647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101541953519848533437152574607340287479154079840343834698213968417610918045509 3114
UVM_INFO @ 14933847121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73853422260734533110469476834146613049964208196902585674630402611106831305823 1297
UVM_INFO @ 5806342996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13369557321663714732430744754794435262253694690165644193901508212102748023065 1126
UVM_INFO @ 1077698769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91789720936837603405635708855647952318793832911769799218764410849029525393795 891
UVM_INFO @ 21261333892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 102999096043095853652229000156090785807711408596559323610094855741509705033567 178
UVM_INFO @ 42267554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---