Simulation Results: otbn

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.76 %
  • code
  • 87.15 %
  • assert
  • 97.14 %
  • func
  • 100.00 %
  • block
  • 99.37 %
  • line
  • 99.55 %
  • branch
  • 95.38 %
  • toggle
  • 86.07 %
  • FSM
  • 67.61 %
Validation stages
V1
100.00%
V2
98.77%
V2S
97.26%
V3
20.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 12.000s 145.287us 1 1 100.00
single_binary 100 100 100.00
otbn_single 183.000s 1236.934us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 8.000s 51.093us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 7.000s 13.813us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 11.000s 47.815us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 8.000s 41.579us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 86.213us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 7.000s 13.813us 5 5 100.00
otbn_csr_aliasing 8.000s 41.579us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 200.000s 111427.505us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 34.000s 1340.516us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 42.000s 903.063us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 67.000s 657.680us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 102.000s 189.285us 9 10 90.00
stress_all 10 10 100.00
otbn_stress_all 163.000s 350.663us 10 10 100.00
lc_escalation 59 60 98.33
otbn_escalate 123.000s 1773.051us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 8.000s 25.513us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 127.000s 744.944us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 9.000s 46.367us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 7.000s 38.080us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 10.000s 408.405us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 10.000s 408.405us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 8.000s 51.093us 1 1 100.00
otbn_csr_rw 7.000s 13.813us 5 5 100.00
otbn_csr_aliasing 8.000s 41.579us 1 1 100.00
otbn_same_csr_outstanding 5.000s 17.743us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 8.000s 51.093us 1 1 100.00
otbn_csr_rw 7.000s 13.813us 5 5 100.00
otbn_csr_aliasing 8.000s 41.579us 1 1 100.00
otbn_same_csr_outstanding 5.000s 17.743us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 24 25 96.00
otbn_imem_err 20.000s 62.955us 10 10 100.00
otbn_dmem_err 16.000s 48.350us 14 15 93.33
internal_integrity 14 17 82.35
otbn_alu_bignum_mod_err 12.000s 60.681us 3 5 60.00
otbn_controller_ispr_rdata_err 26.000s 476.976us 4 5 80.00
otbn_mac_bignum_acc_err 28.000s 181.326us 5 5 100.00
otbn_urnd_err 9.000s 28.530us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 9.000s 24.920us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 9.000s 22.627us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 14.000s 59.905us 10 10 100.00
tl_intg_err 30 30 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
otbn_tl_intg_err 25.000s 118.449us 25 25 100.00
passthru_mem_tl_intg_err 5 5 100.00
otbn_passthru_mem_tl_intg_err 55.000s 1903.979us 5 5 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 145.287us 1 1 100.00
sec_cm_data_mem_integrity 14 15 93.33
otbn_dmem_err 16.000s 48.350us 14 15 93.33
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 20.000s 62.955us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 25.000s 118.449us 25 25 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 123.000s 1773.051us 59 60 98.33
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 20.000s 62.955us 10 10 100.00
otbn_dmem_err 16.000s 48.350us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 25.513us 5 5 100.00
otbn_illegal_mem_acc 9.000s 24.920us 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 183.000s 1236.934us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 20.000s 62.955us 10 10 100.00
otbn_dmem_err 16.000s 48.350us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 25.513us 5 5 100.00
otbn_illegal_mem_acc 9.000s 24.920us 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 123.000s 1773.051us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 20.000s 62.955us 10 10 100.00
otbn_dmem_err 16.000s 48.350us 14 15 93.33
otbn_zero_state_err_urnd 8.000s 25.513us 5 5 100.00
otbn_illegal_mem_acc 9.000s 24.920us 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 183.000s 1236.934us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 11.000s 19.209us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 17.000s 57.357us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 92.000s 1035.555us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 92.000s 1035.555us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 12.000s 46.977us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 20.000s 41.736us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
sec_cm_loop_stack_addr_integrity 3 5 60.00
otbn_stack_addr_integ_chk 15.000s 58.629us 3 5 60.00
sec_cm_call_stack_addr_integrity 3 5 60.00
otbn_stack_addr_integ_chk 15.000s 58.629us 3 5 60.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 17.000s 93.280us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 183.000s 1236.934us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 183.000s 1236.934us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 183.000s 1236.934us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 102.000s 189.285us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 183.000s 1236.934us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 183.000s 1236.934us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 20.000s 46.147us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 183.000s 1236.934us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 723.000s 3180.710us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 472.000s 7882.933us 2 10 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 10.000s 27.304us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
otbn_stress_all_with_rand_reset 73061383938695567545582447294094457560104236056452505348885970306181797291790 202
UVM_INFO @ 1578078016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 34599686512301995220143384016308334686086416750697004044939667052008732763723 261
UVM_INFO @ 1844645568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 61234040811800769443077644659483197820481633901011888197810817175373506262207 222
UVM_INFO @ 969658884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 99393725128555105037889126519877924683051962530744055214045299927225245232021 272
UVM_INFO @ 326285594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 100769709694570312476649652345695204516820640290204363662262973913000925947953 374
UVM_INFO @ 7882933418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 4 test runs
otbn_alu_bignum_mod_err 33201321311098886169820357381143332545964914910019261788841365308169729732073 133
UVM_INFO @ 149647661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_controller_ispr_rdata_err 32611262921590936743801398908306210476152253263355477798769256690449627725659 107
UVM_INFO @ 38876327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_alu_bignum_mod_err 100527906964553496890112810124647166727050042082850724427367079555835020853659 118
UVM_INFO @ 14249113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 32686429573828318809317977265504521056734454903841385969669115474989152849926 113
UVM_INFO @ 81220359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 2 test runs
otbn_stress_all_with_rand_reset 18439196058207888742772739032261523637628344645468467727006538937552484047958 145
UVM_INFO @ 44129420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 112848785963414460807020992387328317014533653458952376064824501653584350810085 287
UVM_INFO @ 3482042063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_stack_addr_integ_chk 60448687432451856068706244452370026366600363033747735565108870237439664600350 115
UVM_ERROR @ 7602708 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 7602708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 60584451220325905368311796771577791334035980439954505180407977052484080466125 112
UVM_ERROR @ 25439046 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 25439046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 92396986188346943983769276201310615477204639472237749957359569868804639125627 558
UVM_INFO @ 3632604876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 32277032423248448403812493457363116465417839920724585584529636195491590329365 106
UVM_INFO @ 2727815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi 59325902120918295484124975648677974483753713553224682676001237550389078259042 175
UVM_INFO @ 154836114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_dmem_err 59497675032670109818536536235611163221372286801431443002816050298980184310627 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1