Simulation Results

Simulation Results: otp_ctrl

07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.43 %

code
81.44 %

assert
95.32 %

func
82.52 %

line
88.75 %

branch
86.89 %

cond
88.79 %

toggle
89.08 %

FSM
53.67 %

Validation stages

V1		88.46%
V2		71.98%
V2S		73.18%
V3		13.86%

23/26 passed

88.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	2.500s	58.424us	1	1	100.00
smoke				9	10	90.00
	otp_ctrl_smoke	13.890s	2410.725us	9	10	90.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	2.230s	211.668us	1	1	100.00
csr_rw				5	5	100.00
	otp_ctrl_csr_rw	2.660s	739.689us	5	5	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	9.180s	637.468us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	6.810s	139.253us	1	1	100.00
csr_mem_rw_with_rand_reset				3	5	60.00
	otp_ctrl_csr_mem_rw_with_rand_reset	51.090s	10005.552us	3	5	60.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otp_ctrl_csr_rw	2.660s	739.689us	5	5	100.00
	otp_ctrl_csr_aliasing	6.810s	139.253us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	1.550s	81.025us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	1.810s	83.803us	1	1	100.00

542/753 passed

71.98 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				0	1	0.00
	otp_ctrl_partition_walk	112.650s	2907.623us	0	1	0.00
init_fail				210	300	70.00
	otp_ctrl_init_fail	8.100s	3106.052us	210	300	70.00
partition_check				25	60	41.67
	otp_ctrl_background_chks	33.610s	3807.940us	5	10	50.00
	otp_ctrl_check_fail	51.550s	54575.293us	20	50	40.00
regwen_during_otp_init				17	30	56.67
	otp_ctrl_regwen	11.570s	5200.640us	17	30	56.67
partition_lock				12	30	40.00
	otp_ctrl_dai_lock	34.430s	5540.093us	12	30	40.00
interface_key_check				5	10	50.00
	otp_ctrl_parallel_key_req	19.960s	9289.470us	5	10	50.00
lc_interactions				187	210	89.05
	otp_ctrl_parallel_lc_req	18.650s	10041.671us	5	10	50.00
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
otp_dai_errors				22	25	88.00
	otp_ctrl_dai_errs	77.630s	43115.498us	22	25	88.00
otp_macro_errors				4	10	40.00
	otp_ctrl_macro_errs	17.980s	1709.947us	4	10	40.00
test_access				3	10	30.00
	otp_ctrl_test_access	25.750s	2444.258us	3	10	30.00
stress_all				0	10	0.00
	otp_ctrl_stress_all	144.410s	27466.588us	0	10	0.00
intr_test				10	10	100.00
	otp_ctrl_intr_test	2.630s	638.139us	10	10	100.00
alert_test				10	10	100.00
	otp_ctrl_alert_test	3.700s	1114.800us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otp_ctrl_tl_errors	9.220s	2956.242us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otp_ctrl_tl_errors	9.220s	2956.242us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otp_ctrl_csr_hw_reset	2.230s	211.668us	1	1	100.00
	otp_ctrl_csr_rw	2.660s	739.689us	5	5	100.00
	otp_ctrl_csr_aliasing	6.810s	139.253us	1	1	100.00
	otp_ctrl_same_csr_outstanding	7.740s	2714.710us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otp_ctrl_csr_hw_reset	2.230s	211.668us	1	1	100.00
	otp_ctrl_csr_rw	2.660s	739.689us	5	5	100.00
	otp_ctrl_csr_aliasing	6.810s	139.253us	1	1	100.00
	otp_ctrl_same_csr_outstanding	7.740s	2714.710us	5	5	100.00

V2S

483/660 passed

73.18 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
tl_intg_err				29	30	96.67
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
	otp_ctrl_tl_intg_err	39.520s	24123.360us	25	25	100.00
prim_count_check				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
prim_fsm_check				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_bus_integrity				25	25	100.00
	otp_ctrl_tl_intg_err	39.520s	24123.360us	25	25	100.00
sec_cm_secret_mem_scramble				9	10	90.00
	otp_ctrl_smoke	13.890s	2410.725us	9	10	90.00
sec_cm_part_mem_digest				9	10	90.00
	otp_ctrl_smoke	13.890s	2410.725us	9	10	90.00
sec_cm_dai_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_kdi_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_lci_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_part_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_scrmbl_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_timer_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_dai_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_kdi_seed_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_kdi_entropy_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_lci_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_part_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_scrmbl_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_timer_integ_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_timer_cnsty_ctr_redun				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_timer_lfsr_redun				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_dai_fsm_local_esc				186	205	90.73
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_lci_fsm_local_esc				182	200	91.00
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
sec_cm_kdi_fsm_local_esc				182	200	91.00
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
sec_cm_part_fsm_local_esc				186	210	88.57
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
	otp_ctrl_macro_errs	17.980s	1709.947us	4	10	40.00
sec_cm_scrmbl_fsm_local_esc				182	200	91.00
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
sec_cm_timer_fsm_local_esc				186	205	90.73
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_dai_fsm_global_esc				186	205	90.73
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_lci_fsm_global_esc				182	200	91.00
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
sec_cm_kdi_fsm_global_esc				182	200	91.00
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
sec_cm_part_fsm_global_esc				186	210	88.57
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
	otp_ctrl_macro_errs	17.980s	1709.947us	4	10	40.00
sec_cm_scrmbl_fsm_global_esc				182	200	91.00
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
sec_cm_timer_fsm_global_esc				186	205	90.73
	otp_ctrl_parallel_lc_esc	49.670s	34255.559us	182	200	91.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_part_data_reg_integrity				210	300	70.00
	otp_ctrl_init_fail	8.100s	3106.052us	210	300	70.00
sec_cm_part_data_reg_bkgn_chk				20	50	40.00
	otp_ctrl_check_fail	51.550s	54575.293us	20	50	40.00
sec_cm_part_mem_regren				12	30	40.00
	otp_ctrl_dai_lock	34.430s	5540.093us	12	30	40.00
sec_cm_part_mem_sw_unreadable				12	30	40.00
	otp_ctrl_dai_lock	34.430s	5540.093us	12	30	40.00
sec_cm_part_mem_sw_unwritable				12	30	40.00
	otp_ctrl_dai_lock	34.430s	5540.093us	12	30	40.00
sec_cm_lc_part_mem_sw_noaccess				12	30	40.00
	otp_ctrl_dai_lock	34.430s	5540.093us	12	30	40.00
sec_cm_access_ctrl_mubi				12	30	40.00
	otp_ctrl_dai_lock	34.430s	5540.093us	12	30	40.00
sec_cm_token_valid_ctrl_mubi				9	10	90.00
	otp_ctrl_smoke	13.890s	2410.725us	9	10	90.00
sec_cm_lc_ctrl_intersig_mubi				12	30	40.00
	otp_ctrl_dai_lock	34.430s	5540.093us	12	30	40.00
sec_cm_test_bus_lc_gated				9	10	90.00
	otp_ctrl_smoke	13.890s	2410.725us	9	10	90.00
sec_cm_test_tl_lc_gate_fsm_sparse				4	5	80.00
	otp_ctrl_sec_cm	441.840s	76338.279us	4	5	80.00
sec_cm_direct_access_config_regwen				17	30	56.67
	otp_ctrl_regwen	11.570s	5200.640us	17	30	56.67
sec_cm_check_trigger_config_regwen				9	10	90.00
	otp_ctrl_smoke	13.890s	2410.725us	9	10	90.00
sec_cm_check_config_regwen				9	10	90.00
	otp_ctrl_smoke	13.890s	2410.725us	9	10	90.00
sec_cm_macro_mem_integrity				4	10	40.00
	otp_ctrl_macro_errs	17.980s	1709.947us	4	10	40.00

14/101 passed

13.86 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
otp_ctrl_low_freq_read				0	1	0.00
	otp_ctrl_low_freq_read	99.760s	62644.103us	0	1	0.00
stress_all_with_rand_reset				14	100	14.00
	otp_ctrl_stress_all_with_rand_reset	155.190s	24162.077us	14	100	14.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value:				104 test runs
	otp_ctrl_partition_walk	15448910196147236107570934504459748154485177168301755541475446869656162615673	160055	UVM_INFO @ 2907622520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	83392566111566666765596295045486955586965332724183469111492538455688661262837	10256	UVM_INFO @ 5200640185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	105922121215091633822729924217199608650582931702355746081661138117224457087646	1485	UVM_INFO @ 102413626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_smoke	104738014051624006980008293029348278488338470511849935811968908956488174862153	2404	UVM_INFO @ 341737320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	92822988882510194268517024893948421725117698587541365696611861514430406315304	99	UVM_INFO @ 119230902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	85092591970437713756213658945251459304923082405473581578415926840592575784466	2356	UVM_INFO @ 1424948089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	64702166520292134744370155653812200434167255482562963679846248528416716641869	6506	UVM_INFO @ 268609452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	48318319471908975002832416180089255945896642930387682745153482361277071515099	267	UVM_INFO @ 55251707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	18571377171254462876261247622963358698207426766409753498762983551034254793301	1830	UVM_INFO @ 1150855146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	78273139489637411721892714751332732620097412593168332745910455363983574784839	393	UVM_INFO @ 55897461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	84040229699611969561213309442173681984922188622180507372510923443925539855643	8062	UVM_INFO @ 298746610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	4098702824515757144073732557992150293801529858056563029240601741454828026027	1213	UVM_INFO @ 138384856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	78129227844612342739484358826833715137354721243618387678542589514693271238825	2620	UVM_INFO @ 215978492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	79336870529394984328426132469565783210261823587367046954851762820384762922269	1001	UVM_INFO @ 74533023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	19341334389041107033940006480480776184418483576135753808678739225394556548493	920	UVM_INFO @ 70876622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	23233403381909794453876396184293858902120310668331207293483879332462504107960	1307	UVM_INFO @ 111097427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	71422609909905715036681852321067157917691816310343651260475217862694755422049	2860	UVM_INFO @ 164339720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	13055785806254361361029282409370307439676639135848034839850267427172108489734	9534	UVM_INFO @ 303296737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	23907915425999491750357782777126518672498454884328658158893729569663990785204	1152	UVM_INFO @ 110553102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	56580318934317502213031054409233092098483483809141737006612908499006157722403	2553	UVM_INFO @ 322947646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	66959431659044437811811785632212823400122604049675477803060031487243725515285	3200	UVM_INFO @ 97018484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	52886355212205435279825490146194297662621495313248456377333464652564834284732	1202	UVM_INFO @ 54377589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	50428597884100278834112394743108323073682485724459961907508534779939729378815	1341	UVM_INFO @ 53494700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_regwen	13988043595322700307248641196326149130696870682112628961476680354337902572323	2362	UVM_INFO @ 109752652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	83167304928644490463275918595071448897996881848408730202272967242178330378824	1405	UVM_INFO @ 143380311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	79087756601335637620385272768973497564847115203836571181208783134692371696204	1057	UVM_INFO @ 215759726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	58350494755372907305995213674686215319208058479943538642967550639733387515440	325	UVM_INFO @ 579572128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	75369370698631459688008609989959519393136244665100724376113948075565081972017	507	UVM_INFO @ 202596639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	56125705653514997885740228992343568023171265790811819513430707642654754324132	1869	UVM_INFO @ 81076662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	2407003086228919326511163766587668875072789482299108578433855801004653028980	341	UVM_INFO @ 563255763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	33631040986915810748918760766789911444340202041273134265914742610300825920462	141	UVM_INFO @ 31410887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	14226734134114502414835911428490585648966783391956274411014346503650879721441	613	UVM_INFO @ 97350026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	63249832271866890111325203118432621592402637987460235777103778313784988939798	341	UVM_INFO @ 39930531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	80986544036875773408038634822396457022647195092100577193895011214561079651942	223	UVM_INFO @ 94280294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	7587346306678064229964389305373898607919492358560320340010219782081145488611	225	UVM_INFO @ 102868960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	86802582430954246407525765201437139409003799184101546254232585930440282849948	2241	UVM_INFO @ 267387468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	96043268779362683158967437946560557393405517340436206782808418681601754538162	675	UVM_INFO @ 978077714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	10436452188984609382147993698752900621711295265162031696131410286433456637756	367	UVM_INFO @ 670800119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	45682089628805156572244747522955578972282019054888108004004250734940627023601	1437	UVM_INFO @ 222050310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	70277264417870441234912581703259187020103478490909975368109372034416826391367	927	UVM_INFO @ 851482344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	35858581402604923087698725819489785621019336250230230602175350604048096659828	349	UVM_INFO @ 187107538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	76152018814761666181102822359264460354963365173726699642146948726733161249093	2189	UVM_INFO @ 65203047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	55135243045832765335767609289632066814468565188306236884977769310499424073103	225	UVM_INFO @ 99462585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	90530992447240942701644009585517086370241045439419929393337163512508183436364	1203	UVM_INFO @ 49648912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	28424969295400013226834908445994037117751617286051464203565389451321954075304	2937	UVM_INFO @ 79244308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	3593681378969617804575901623066886505137319396913753999844481378966898743394	593	UVM_INFO @ 64867040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	98057012988581940837460935142918001686147419129143880553154415572075676860519	267	UVM_INFO @ 912152029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	71422674707111865662555477716833223073455533596678454399330286404895592972121	659	UVM_INFO @ 167445416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	35055733732040486034442390671458318989035945880526844435999521179773036787750	539	UVM_INFO @ 131484794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	105178842989561185742352478827374044775581671713753948385895316001765547070479	1027	UVM_INFO @ 100887943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	18535085666842553918776515504961768196036252112466043265860113072996210583503	857	UVM_INFO @ 108763203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	12585127818069377981269722873724350865809912072004918225216132725025333777760	139	UVM_INFO @ 82202926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	82162112871556102252116321382072257740235523659838278167343256611407630076469	99	UVM_INFO @ 36154500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	111087070201004450029569111188751251330421467325523604330718236577660388173536	367	UVM_INFO @ 77581062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	47850836601635875786124159908774987137996053822370621058910648998613251639604	843	UVM_INFO @ 43846126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	97459066354385721179727536500626393701948172366406899451002547953592456906728	407	UVM_INFO @ 139478554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	51962173987871685624944191360587512186265587071391562573167143368697119288740	1607	UVM_INFO @ 116451804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	70077584018109159534964837706102240874466621257792707278950687103141240138217	309	UVM_INFO @ 215427151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	63107508958710547993004122276424432269821890037571438733845778904297202262149	2411	UVM_INFO @ 83126484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	69223311917609609567570693056470199338507327863657106016416381284549141657070	667	UVM_INFO @ 42528514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	28257996005991726973707549703002593359030009002398163091534101345842535159884	929	UVM_INFO @ 1019837269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	59252324490071876937701484150031811140154855309252590281255897646858470576295	899	UVM_INFO @ 46233872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	86993951355263201740679553126018228525040692195730624838339665684717306496995	341	UVM_INFO @ 575340482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	75689997010538213190875248900498565191181221926943928544361654580219633601222	637	UVM_INFO @ 663728830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	4528072478546181489769493817014907470272100156625187648709855894105605784499	703	UVM_INFO @ 680948412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	69510846755568013594320751954786164093618656893010314282088893727576781674089	753	UVM_INFO @ 79473869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	98743000060453467444606427825201928147425667371399092922234526787851523592464	1281	UVM_INFO @ 828295384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	22495123402885502630498824657486938317853697017441614142131051921941864773952	1259	UVM_INFO @ 264089688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	37442405182764192437096696612694267565598807723774483233848919213146177322184	183	UVM_INFO @ 40632467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	57542488988792289530507112886100775793631853346608716103465635549030149178839	1597	UVM_INFO @ 58111457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	96998996955333772631898305973715399649346271241478435682171175040729393829894	183	UVM_INFO @ 540708325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	35909748222152456229818057130629573229031394136333288698791763718195946247051	1395	UVM_INFO @ 163824362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	48835796193077555981970269660960918956313987360008149865984606005601997354954	1979	UVM_INFO @ 1385815993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	97046025097069470975226332938899993069154971405331734628880331984375352791496	99	UVM_INFO @ 510674849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	67724120438777226638128172405900503702935571407986180770160524518862624444194	701	UVM_INFO @ 83875019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	92027972505907245499749935399627048158329626141642894142292761149414330933246	367	UVM_INFO @ 100904350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	78429501574460219718048115185632231655779940938730323126612810999329213004579	493	UVM_INFO @ 627421118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	63390322240244979243996388962047032688779251205293221749834484404829076532402	905	UVM_INFO @ 180755463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	112598219721675612857378143861831896546901155201833497892760718769337641339640	1169	UVM_INFO @ 116450161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	55447824551289924517822749504818756307173641180200932611422977064246757880154	283	UVM_INFO @ 546856292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	51962170887385395671944608594855369666186543923340978923204857547164780796492	559	UVM_INFO @ 183954553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	9600354786914237155430296484147807792964615310694952958500037724267876265715	141	UVM_INFO @ 56294071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	58255968255192735374801377088761498024352148716300995022218306221809962446931	657	UVM_INFO @ 97561695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	47022987775439416975307766085782611794279610822090829595926192287493878839626	225	UVM_INFO @ 92507852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	90130708530453215590335739246108170790899595327611779031478884459800458086279	225	UVM_INFO @ 85451439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	90903390077823759948047384810329089572235840264082569276503578161547597943939	1501	UVM_INFO @ 134764075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	7660369371365744390319585336546957984264393422835584231507186794711494887577	183	UVM_INFO @ 128590628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	79059213862933265647548568968693438451433255119423099981424189930675948389506	1163	UVM_INFO @ 106320652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	111248925940094943473014190605422991869075952837583755930777458516522192280448	141	UVM_INFO @ 75212695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	83055652963891195007012016571474826487436720506928492899643304157688676596580	99	UVM_INFO @ 137458061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	78037748429198879071946023617168983158744847809730053288833883617876254534236	691	UVM_INFO @ 58215112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	13448313206658567415322675165900089565520591930288523236453002393368234249968	325	UVM_INFO @ 78915122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	54050156535333748742936035831953058009521864247309467916940959105844941751135	141	UVM_INFO @ 131737911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	62772682211077300896592467242104473317848609783234349621134202639610467647963	2019	UVM_INFO @ 64022992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	94929120348012509898387135320250008281056756013324281286157275239988979164401	1097	UVM_INFO @ 123774143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	84692660005309913354983422480096386550785897859896024279927216947580865910868	761	UVM_INFO @ 85102248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	46184181226978123475877620569979554521820037968034000511114328497426525917367	1007	UVM_INFO @ 139718032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	36677180665105324254695514812612071941574161341216859996731654976361058934024	365	UVM_INFO @ 247222408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	87775855752466578059855812299316152946394960885118869514400783799936921669009	1359	UVM_INFO @ 108785065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	19120344385900463163777982277817855927378863047842552690909244889621671282558	2335	UVM_INFO @ 107652275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	2907962210492013033662425488222470146980837196301002693702801925353564099055	891	UVM_INFO @ 961546335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	38341948219186458589111788273756052872764503754803767100060198199750034866953	883	UVM_INFO @ 141570715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	77496629734512865498938959687682819617710287454698374750628932371418084615176	517	UVM_INFO @ 39442190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_init_fail	95247951778381785643201755953560266551234493173323650714465544660378683843231	347	UVM_INFO @ 140631911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.err_code_				68 test runs
	otp_ctrl_test_access	60760066352128366439823818782910207253126722590592279471027767716101012328291	3023	UVM_INFO @ 335281489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	8014378341618638256009173694963748092141582244920599061054312808664751049120	1729	UVM_INFO @ 772278610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	71388737937199257710499836550380156335642566251891096064421371408781625290280	7291	UVM_INFO @ 890170713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	3797658536390623963720584670408151632002933692251791293438223479115995678510	2790	UVM_INFO @ 74923793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	49246040943317674512405940047546939812563206480601912531152671811984737727247	2320	UVM_INFO @ 290007826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_test_access	86970661677045529185354812898058207987870778280413447959193674584298291629809	3000	UVM_INFO @ 894957103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	74802406939111382637271034651906177373931626326561175066645234162748124009743	2812	UVM_INFO @ 301734600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	791466864223841382536867707455896197868772149518430150823252050894683492571	1942	UVM_INFO @ 1001376333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	74585606833389909744743689834264801568376684720843004566688462109983610203418	398	UVM_INFO @ 379759110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	94697497913214951622973986903708058406812410013486223818729478721102794841442	964	UVM_INFO @ 393504014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	77472646381835995334022980433290615566230123068214174261145154685975670094881	5432	UVM_INFO @ 1851824187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	29270560850962110039778129494697873278301066468900553510580901165937486344329	5329	UVM_INFO @ 373667668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	69537742655930749486781558534344520223214441896375748852814194234937929757041	3164	UVM_INFO @ 97995993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	3096568473909036078172380962605606975107080665300849432976060889121790945007	2196	UVM_INFO @ 132420679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	105921373573583047541863197105158723753664915122165992366209864889052964754133	6251	UVM_INFO @ 266691217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	16624655505560699782594132545776125499298584011659218583737493909774840997080	9628	UVM_INFO @ 874314175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_test_access	41866144606066898550983958303199842292217000245688135344300152607068773943232	7073	UVM_INFO @ 389308896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	109582462748555524915933891670664976620084491308839929829962328051942094414798	5673	UVM_INFO @ 6928791130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	26409122757349262437757130931949220054868326791637636452876490291621008662018	5612	UVM_INFO @ 552378116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	102446998379447357813092574164769303694888437175222298611723700851886505932294	4022	UVM_INFO @ 122807173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_test_access	83248981367680787349024316976467192732270500723093932567539200360681887963706	1720	UVM_INFO @ 1198070257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	40450386074761116809565981713943179729747384800424672943818348105045094468190	9313	UVM_INFO @ 1589711119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	54051519433734528387738798246171543409128123843759206612490740383142522635723	8211	UVM_INFO @ 1995914552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	24674019439758274486757917057154632182455815745944628327086627520979406989017	5653	UVM_INFO @ 646263882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	104224035752325416370738685585743861269427788525939157718185553841723038721054	610	UVM_INFO @ 152876382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	71005994196402833064888469125010508070593106182560617967173419321252946261866	1612	UVM_INFO @ 160450795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	9353051692419062758498314672660355824153446574283319262101299128682029922101	11564	UVM_INFO @ 924541758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	15015396651330467073401520409539840350825710770003635148556226883735076211563	2878	UVM_INFO @ 477036855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	61451422574267286321740827487320199673145615653142347375922613518628554388570	1207	UVM_INFO @ 154686324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	20502821223650090808589730911688855083743541532800569082157620293365788245571	596	UVM_INFO @ 270940917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	5496026954702354208061224259821009656216933447526477016814254520805143908858	4258	UVM_INFO @ 334497824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	52785703682181561469452226180353324524598353641919445977789997203249859272965	934	UVM_INFO @ 90571047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	101113902443304813672837928229984250034586632682474977307084618608659472053897	2816	UVM_INFO @ 142659376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	87065927794236914081421779458899063087829811940627825465965996984261618021523	10133	UVM_INFO @ 1225284927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	50730506745834113900946891778014382507337309678489259667617772517470567925236	214	UVM_INFO @ 935091720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	13579253616539379860015208776041393900067968140989940537124578532810947013735	1802	UVM_INFO @ 1177958099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	17164268859476118032906147020091419933146735177153341690990373150080537034392	8134	UVM_INFO @ 10203526492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	46361566071040685193281273201858641589422158077884344483070079180807752024637	9269	UVM_INFO @ 1753316690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	38075413790177394869603671458612817206555526752526197496426303207573065426846	15190	UVM_INFO @ 1149727377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	47213973443253762274976553830472507959249187945612970463940885764532786423565	208	UVM_INFO @ 272599508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	107594806791445232148884285429052489283230027416615366680070677048085731635351	9954	UVM_INFO @ 1509063727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	55177585317378680032809383041720300766410108089942174217387212537941879328223	9810	UVM_INFO @ 3279371807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	88349832709636563085662987783003770341500191813887611878458192916118070158727	8859	UVM_INFO @ 1921710266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	105337483167229381533492744169915240939803386047194259463700836607385424139124	2926	UVM_INFO @ 119876695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	84472410582171197027105100340188899405085593246114648669444168459271102332115	2676	UVM_INFO @ 18360841783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	31389057165724269663729212324915097923708725006499934952365700908249121780804	720	UVM_INFO @ 216860577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	73624943627422186473635680126246245705329970318687029098012520218021350817909	5010	UVM_INFO @ 1691154186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	113387846958813753882658067697306092016814364803101145484222403592337499682317	3152	UVM_INFO @ 194916025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	16419483138769359050262395299269495038035891614813935751735233446345708912868	2011	UVM_INFO @ 457058500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	548904763672767805100841052981623683486370457212642288554957346043641851095	15058	UVM_INFO @ 6600046516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	107035826567343277786075149101858102508815089487036842798047983397940618994900	3132	UVM_INFO @ 504031117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	51263102835846998490174543553423258006411221469688317841720959029063032768104	394	UVM_INFO @ 252877271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	62937841087172851795445198402026236925778631607632321046812918153929408664055	2084	UVM_INFO @ 65432614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	98204540677822815785568479042088095174392521808516516183873033255506906448308	1019	UVM_INFO @ 3436282091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	11715087029402610301206990753678387122201821003668465416713339021727147389922	3194	UVM_INFO @ 156086704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	96907898262467324646822023590865843696569342527279986121771988738159429950513	4060	UVM_INFO @ 13909455910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	21294929981518123896386698870896341820652320379775891027016650594670118312878	2480	UVM_INFO @ 167682795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	100116319309263265510450823167489394886812910445876922116722569564207248645135	722	UVM_INFO @ 92938412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	110210172901902157743408796201132420410820581227510051020696790785657967034391	1104	UVM_INFO @ 209423134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	112320339006561000377471695213787327523338258940626877091310778067786688440211	1520	UVM_INFO @ 131276944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	25557673524769368862594981952291373237321622387247682089777266380080520246126	2164	UVM_INFO @ 82619324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	75996798254904631518721137053090408580486562225850021303699903385126456712089	1026	UVM_INFO @ 90674066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	46550476190715259152103556135733047354309758440853103270929104024989313022691	1566	UVM_INFO @ 485301805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	62094445936700270257774269033850385235187842689275116351824797664616374196904	400	UVM_INFO @ 153818677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	5512492759229828522359450122487280235579728841075986848456893781831148514157	3770	UVM_INFO @ 1449284005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	74822604819445674530214290566751843796214325475791592625061529110149440986744	2372	UVM_INFO @ 1083399200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	55018638910950602208332829602625275476870342210692030516431491952487495970457	296	UVM_INFO @ 168146598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_esc	57993855653599123658844982110045632888169244790413294387954804960467056768024	1670	UVM_INFO @ 125845143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.intr_state				36 test runs
	otp_ctrl_parallel_key_req	36631798195762998185773557034435535375400544615272653927715888520471888067783	6641	UVM_INFO @ 526715431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	10007846731308893126224542819770777109376572642338757696023337276826251161749	10314	UVM_INFO @ 3590914341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	35648761011600415535297551136797615130847759510010493904195470633790938220345	6593	UVM_INFO @ 345517531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	5136229410858217501444594697971063858016748180801654164280156941890049549160	20274	UVM_INFO @ 27968544437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_req	97915308872694603123364312732506512064353919023340066759902511255998084677889	4777	UVM_INFO @ 261401167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	9515851603365330757851031098020390547839338036321760629924188697499619142534	2018	UVM_INFO @ 131220827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	41229992673735983129364449769921686632414229521940074664292541084362874990544	11944	UVM_INFO @ 2744671875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	28360202799431102668523314815377877730632141266900688622120658930320617103247	6591	UVM_INFO @ 1002140828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	113883568119613484617520953035457030712343352382643431885612482561998756218734	1628	UVM_INFO @ 15402717115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	71315643450161230542011316235710732278960498513679844252338098828794005251668	6957	UVM_INFO @ 2398872998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_key_req	89126478221504538325879621658072635264971660655569132234282974210288571178988	7253	UVM_INFO @ 184243861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_test_access	71353528741735454957355767648166480229074878648483611937232901992951369805541	7304	UVM_INFO @ 2246089235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	32449166393852925349945653065736095278986834590311080432637034393225117134106	17101	UVM_INFO @ 3587426821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	47921417049899991247850918937108430109642253786900307240448461103174896879835	5047	UVM_INFO @ 1048158525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	80774510758538877993311616939216947119783590156188806570564023685954655367985	8633	UVM_INFO @ 2991334625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	42930511664159341993738002189141506087091516708496730714389616250850215601679	9666	UVM_INFO @ 10629741368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	68142324176762054185541830407772404192634147968309190072960438633030432700797	21314	UVM_INFO @ 1897473502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	96506238617987882039620284909733563322150618218515418608501447392272619434835	17866	UVM_INFO @ 4317690404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	92312532674854030547138028442951490105003963014461831598596181975578161350610	7696	UVM_INFO @ 619544537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	60027699894015634653650229483253358617201273174217836633181290754304908519895	12036	UVM_INFO @ 5127994837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	59949220383733463900867168701034045391030264289327531786016686252094029763532	2741	UVM_INFO @ 347013808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	114049850973388273776444163542877866809425826725354877643791789752113984494392	10444	UVM_INFO @ 2357089628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	112951074998376603560135729197434913753132687872829105538505069525451727905040	8123	UVM_INFO @ 1109546671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	10513096170577489073243968649098724156195180039598821153360374420307508275127	2066	UVM_INFO @ 740903904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	40481052490100842799560240928778485094207044884022952114775867827454268597753	4037	UVM_INFO @ 2548071937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	70161299304704084354197300678455630101644170988979755619566422116626384026739	3522	UVM_INFO @ 1381858394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	74602678941203504885986804137990268925463815389437066401445898320987775013159	23598	UVM_INFO @ 16902881996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	36605185631490742382120161281814562868423791245039311256196195420295112857285	14879	UVM_INFO @ 12833047400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	64788227622249627707223354148319428394464464102134778964042476685992207098368	2628	UVM_INFO @ 1671602049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	1957178893598186779839275411456170725027065411850520032175621813117985642237	28286	UVM_INFO @ 1910899169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	80719359734495323903673269981902765060995871724528984511480994777038956427695	110	UVM_INFO @ 564101500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	3110391756166101581489827229883285291575027514907791357033088410249919504042	64109	UVM_INFO @ 3460591503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	2358036133952443996504559241090351699597788538386857601284743389310938686709	268	UVM_INFO @ 1704962776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	76784936384560368400135738569089671932037606870704142363837351720114515378473	16405	UVM_INFO @ 3464888757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	60123082679902512189958086294211714975749694009354544137781962517221388925972	10148	UVM_INFO @ 3043555552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	40509693518806836964937022102255650842378600300773358772062135795392952463475	11016	UVM_INFO @ 30585679054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.direct_access_rdata_				29 test runs
	otp_ctrl_dai_errs	31441532155948860113213012668073722623854086999113043865682718712102723171143	11878	UVM_INFO @ 13950135890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	107353404617177184879066265236990162935749362470715852285211973489841589692489	4501	UVM_INFO @ 463168249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	40747344942439913396948162745847035032033972331725652889945330047650642444290	3579	UVM_INFO @ 493525247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	51150565581396311088519379795420190014347516913753344002555241973863017666390	1409	UVM_INFO @ 402398360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	64549690582627032257889185170239285924089053470747621960295909368717976123472	8876	UVM_INFO @ 928716790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	72996917967459642522934496135006876648605063675510634817383298218280668073644	370	UVM_INFO @ 213366263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	50759315845247614947781952213633998793420076780403350872283853714968831913955	4668	UVM_INFO @ 903736511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	90602289477624753485642063998206427156791823282000810595476524185912163918050	8530	UVM_INFO @ 1709947355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	83339161002839049378223518141362489886644813929690174185186789298073444005419	4766	UVM_INFO @ 6802272633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	59117487206804257478941518916742471323497937067641749738997597573723537848399	12452	UVM_INFO @ 936053083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_errs	37254571886867197961667092780207572475252338841051025100980400054492827227852	1836	UVM_INFO @ 2419531979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	2331307904295285139402614555631661652501978163719329313560890251284637708428	170	UVM_INFO @ 771979145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	74684555648160259858746943433186130182194912165485376686916627539234803273393	2299	UVM_INFO @ 3748800389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	79396213485885311398825221619666277947951841034042268472220078960633161541800	1692	UVM_INFO @ 241565487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	104362512703798732973427033030891206122535884358690700954271560498379849869750	322	UVM_INFO @ 66214007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	97438080633096645253839911832422883379679647271232638108995838785890472405500	16570	UVM_INFO @ 618181410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	46722463757637557281028591752597049019029197345573365518757314838900447593976	7947	UVM_INFO @ 409988661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	94851826192412196968943481701679971724225122502039739197766857081953544277329	7758	UVM_INFO @ 370926930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	104710217169893065272342582719467744431472197284488687126050344168899842174621	4759	UVM_INFO @ 805601944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	106534614082001887274720423353109075341247713881630874265202907457753104435	20511	UVM_INFO @ 1656310528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	31495104860248303524408167142058365841033868907058753818202597089796949489723	4909	UVM_INFO @ 5278437867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	45347686729321077959789925313888216171061193710445710762454450238479710387368	3952	UVM_INFO @ 1787065267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	112452779199773628849425192055995472038335230277557936265629215127251900785409	1990	UVM_INFO @ 160342846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	14379445301712286198091642898954576474721354946458983198137397130542089997576	17882	UVM_INFO @ 6566675649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	11538840218823247743361777727585886065213421909704029238125662517450246011891	4637	UVM_INFO @ 1529599699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_check_fail	55767379605094452100290658351335762774246681311711916832775675909096851312979	2066	UVM_INFO @ 628758847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	61780350546488920542454463816333681471630394566055839464903966472844180268362	240	UVM_INFO @ 48387721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	88497615701924020850242231933331740241880278338383543208013892114158181219940	21965	UVM_INFO @ 13365346298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	43494688755875914540534629943683869538036588547567661743284984833194774972968	256	UVM_INFO @ 138825946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2219) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =				26 test runs
	otp_ctrl_csr_mem_rw_with_rand_reset	90584215167266964781754309183536862805112960401092201671869947951921024517753	91	UVM_INFO @ 31147820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	82688841469071538125001862470106577846354650240568733534952640418397476974202	155	UVM_INFO @ 1625732463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	9295539185977442785141103538131234824155892319124693000470144253782216093987	208	UVM_INFO @ 2929071897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	105084181665287610310556013785986082875464307001285711476265064702258971522112	91	UVM_INFO @ 30098019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	103706498685857972991728725795049705106319123007424733074220757670118835723419	91	UVM_INFO @ 60000751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	60619850505980082619393475498893652107495458955661285717741042291489949114156	375	UVM_INFO @ 1174296114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	22319050958102704838104543150304289294385598232774025899990283778433842819680	166	UVM_INFO @ 1016984875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	53454683218108495956395257410983698513168354604075179796461882988955118384509	91	UVM_INFO @ 125641460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	2167329974950824145018396657833361974777084829254757011164751165911538383862	1079	UVM_INFO @ 81473004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	15203779919911324886855090902634111551962341028450335874957084601295721469061	4104	UVM_INFO @ 1148640384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	102909000670778262450689062621644542494046506176688975077089129125000588197613	157	UVM_INFO @ 2078156648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	103592330258726933127399712298162353781992683696491858714008793195849427916913	16921	UVM_INFO @ 7228331936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	42148221816526289240823813219241937576424302382758547801314071535413462776515	211	UVM_INFO @ 108655974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	82342735802350281482562353305870963057588898122982174213781334340005516567428	21615	UVM_INFO @ 1744382586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	17404527720638458358309665785397951637736866374880869888513201769771812786287	91	UVM_INFO @ 500834025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	60539866577320554982776923223531068400144663202495595100077379744033347921873	152	UVM_INFO @ 706230839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	9181298974462712094400298792430719334421891959107493579660230782575112070181	331	UVM_INFO @ 20850077578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	36217483678455377128192275331284128178710091012930854366186097433755333732524	29454	UVM_INFO @ 839023502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	76436222444760112787571110422304809059677496021964503215646707994722238976413	9317	UVM_INFO @ 24831919298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	4661999068728409461246342981890771035900950449738778068327275272696889278127	91	UVM_INFO @ 30572220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	95488237607359367773187807552785886346719052548550889910556485215483650256318	92	UVM_INFO @ 31083774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	55880536923999432894337578855480702709373049383802379589767092221766265388466	91	UVM_INFO @ 502095752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	43323283141422888345381544216769656794037279437989897653770778901178974979955	422	UVM_INFO @ 82716331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	63985734524273165040703192812144328535379440102007230132070262116567979225656	11580	UVM_INFO @ 8395530622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	62849006488459983492487729165390158064207610586543155576369202726162109307576	10223	UVM_INFO @ 2196207978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	38906820764775322296058357508816766783770517979714116989973865360516603889932	92	UVM_INFO @ 34664623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:677) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: OtpErr				10 test runs
	otp_ctrl_test_access	28017090341807473675641488899839039454455174181673227723679727247936031996778	12700	UVM_INFO @ 362954903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	76737863963349972653967924140307604013304178687315287106203886449264185870873	7794	UVM_INFO @ 746288118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_test_access	41954953665047915627960683149861358184053652518677195721636879314767062794606	26789	UVM_INFO @ 2444257536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	10468136415225604793525635927850431689746098814570183410089942116317311239915	7889	UVM_INFO @ 540212607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	12728519196746609956865512918010817287782334883190250617130855712179824861102	15140	UVM_INFO @ 1266311944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	30007594871729204526970892315973150216549727988937562699629913365626547779110	6826	UVM_INFO @ 2814120378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_background_chks	87906403234726015888339473242625638396932506256001710872124806054802410027628	16873	UVM_INFO @ 4908018877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	86890572190010933217416866844651623261618097244925612090818951410461529494356	3421	UVM_INFO @ 148386626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	58548265720824184375641321285291098455250439204160260895636413718641219398215	18340	UVM_INFO @ 1236688896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	777464583587787951859179446009584704026256048191337245809308560254754126583	13150	UVM_INFO @ 2355813841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:964) [scoreboard] Check failed (csr.get_mirrored_value() \| status_mask) == (item.d_data \| status_mask) (* [] vs []) reg name: status, compare_mask				6 test runs
	otp_ctrl_parallel_lc_req	11717980729862000630241045719090480232586812282273169733448762251987096288581	7272	UVM_INFO @ 1054186120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_dai_lock	95686257128473715551779108089859003086092008486371391372376525965412676190857	4265	UVM_INFO @ 1458250679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_req	95114532661552236914167121782078128030572055663785883155011765830341456384262	7067	UVM_INFO @ 780922793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_req	30754873718830009348671427799569779199030869429982081773878653904902355662587	6093	UVM_INFO @ 288388902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	1094398225013379128959942157701161130157560193538765592366838791072857339822	6524	UVM_INFO @ 7298532069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_parallel_lc_req	61634031070322694595877711507162858792043791525019734845366908185970579921962	8230	UVM_INFO @ 365622307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:672) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =				5 test runs
	otp_ctrl_stress_all_with_rand_reset	100230959454623147338492418075722473127746941160847361502698333168424245821674	431	UVM_INFO @ 126139112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	79600517697507461785312032294060752296870777850003420713025646327921760527079	91	UVM_INFO @ 34993003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	54880389776471754850860338259631256889638918617055556167635953081685497818537	91	UVM_INFO @ 502772209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	110585538433612963963672170583704883930798720761032745648002702004354723234617	62204	UVM_INFO @ 3314186407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	16904399951790212244320379812390148667952001728942106343014093695623030744808	6054	UVM_INFO @ 1476169890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr ed* rdata* readout mismatch				3 test runs
	otp_ctrl_low_freq_read	73339466544539823528936484117083809479413384575274771447875830274063575039761	89	UVM_INFO @ 62644102533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	86718155935515306322249513497203707644931788687607469087566474936133686977802	22418	UVM_INFO @ 27466588127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all	30547090260790613403246616311974181157602819056908851450714654749241071392605	5573	UVM_INFO @ 70137382995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred!				3 test runs
	otp_ctrl_csr_mem_rw_with_rand_reset	82248016116739798995198550429100574271272869894053026982450053234944712417547	88	UVM_INFO @ 10005552044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	95030827891533581176420921933318057491169561056549682350312993707216623879788	8129	UVM_INFO @ 10658125305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	28700166823327642631824107191034549596679228161759480242201593384400871154541	2689	UVM_INFO @ 12590228442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1326) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen				2 test runs
	otp_ctrl_stress_all_with_rand_reset	105624684813711742480199120804962362002584639428046301396935237736145362123841	8268	UVM_INFO @ 19328029121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	96446999102361892467618388524547643484289628908552036840511419297275202169598	4550	UVM_INFO @ 1046313435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	otp_ctrl_stress_all_with_rand_reset	104278134636345964434388927301513679080464560454810885300352038757998575524373	1808	UVM_INFO @ 2577913503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	12876491537951350933891887665495643154301190691605985900719108058103413935744	13608	UVM_INFO @ 21790603838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr c rdata* readout mismatch				2 test runs
	otp_ctrl_stress_all_with_rand_reset	87611173737354604607676395069467504107313589819421831292863485746301876623122	94	UVM_INFO @ 7342977036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	22838751825736952902498450059862862616224958222360184892562297111908379844208	95	UVM_INFO @ 10035445298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [] vs []) dai addr rdata* readout mismatch				2 test runs
	otp_ctrl_stress_all_with_rand_reset	71186042439111496984884605447865354648825530168845460791646239769067421317240	99	UVM_INFO @ 11363320049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	93062780134346857335869061202685746556154389365282768054481263897890210796547	97	UVM_INFO @ 10779702766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed				2 test runs
	otp_ctrl_stress_all_with_rand_reset	88509755597360191057407325154396772559930701439206885673907290486405189809743	587	UVM_INFO @ 171826148 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 172000064 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 172087022 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 172130501 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
	otp_ctrl_stress_all_with_rand_reset	83352875673139896170784842266626779672673683831033554662009623197536393595656	6562	UVM_INFO @ 48286951744 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 48288785081 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 48289451749 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1 UVM_INFO @ 48291285086 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	otp_ctrl_sec_cm	27228587575929801501030040488804454014133548562433961585097766146340514385706	2825	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1365) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_check_error does not trigger!				1 test run
	otp_ctrl_init_fail	87116820508993870049023252139484290126738446492423430636647731387833393437585	1404	UVM_INFO @ 3038908460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---