Simulation Results

Simulation Results: rom_ctrl/32kb

07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
95.63 %

code
89.94 %

assert
97.67 %

func
99.29 %

block
87.78 %

line
86.71 %

branch
88.38 %

toggle
84.69 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		97.18%
V2S		66.10%
V3		85.00%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	4.000s	1634.522us	2	2	100.00
csr_hw_reset				1	1	100.00
	rom_ctrl_csr_hw_reset	2.000s	68.798us	1	1	100.00
csr_rw				5	5	100.00
	rom_ctrl_csr_rw	2.000s	120.848us	5	5	100.00
csr_bit_bash				1	1	100.00
	rom_ctrl_csr_bit_bash	2.000s	130.024us	1	1	100.00
csr_aliasing				1	1	100.00
	rom_ctrl_csr_aliasing	2.000s	101.663us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	2.000s	66.095us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rom_ctrl_csr_rw	2.000s	120.848us	5	5	100.00
	rom_ctrl_csr_aliasing	2.000s	101.663us	1	1	100.00
mem_walk				1	1	100.00
	rom_ctrl_mem_walk	2.000s	63.564us	1	1	100.00
mem_partial_access				1	1	100.00
	rom_ctrl_mem_partial_access	2.000s	49.841us	1	1	100.00

69/71 passed

97.18 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				0	2	0.00
	rom_ctrl_max_throughput_chk	3.000s	163.601us	0	2	0.00
stress_all				20	20	100.00
	rom_ctrl_stress_all	9.000s	2610.983us	20	20	100.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	4.000s	385.163us	2	2	100.00
alert_test				10	10	100.00
	rom_ctrl_alert_test	3.000s	54.976us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rom_ctrl_tl_errors	6.000s	369.144us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rom_ctrl_tl_errors	6.000s	369.144us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rom_ctrl_csr_hw_reset	2.000s	68.798us	1	1	100.00
	rom_ctrl_csr_rw	2.000s	120.848us	5	5	100.00
	rom_ctrl_csr_aliasing	2.000s	101.663us	1	1	100.00
	rom_ctrl_same_csr_outstanding	3.000s	69.842us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rom_ctrl_csr_hw_reset	2.000s	68.798us	1	1	100.00
	rom_ctrl_csr_rw	2.000s	120.848us	5	5	100.00
	rom_ctrl_csr_aliasing	2.000s	101.663us	1	1	100.00
	rom_ctrl_same_csr_outstanding	3.000s	69.842us	5	5	100.00

V2S

39/59 passed

66.10 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2187.000s	1000000.000us	0	20	0.00
passthru_mem_tl_intg_err				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	10.000s	1096.882us	5	5	100.00
tl_intg_err				30	30	100.00
	rom_ctrl_sec_cm	120.000s	753.456us	5	5	100.00
	rom_ctrl_tl_intg_err	31.000s	1895.984us	25	25	100.00
prim_fsm_check				5	5	100.00
	rom_ctrl_sec_cm	120.000s	753.456us	5	5	100.00
prim_count_check				5	5	100.00
	rom_ctrl_sec_cm	120.000s	753.456us	5	5	100.00
sec_cm_checker_ctr_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2187.000s	1000000.000us	0	20	0.00
sec_cm_checker_ctrl_flow_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2187.000s	1000000.000us	0	20	0.00
sec_cm_checker_fsm_local_esc				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2187.000s	1000000.000us	0	20	0.00
sec_cm_compare_ctrl_flow_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2187.000s	1000000.000us	0	20	0.00
sec_cm_compare_ctr_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2187.000s	1000000.000us	0	20	0.00
sec_cm_compare_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	120.000s	753.456us	5	5	100.00
sec_cm_fsm_sparse				5	5	100.00
	rom_ctrl_sec_cm	120.000s	753.456us	5	5	100.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	4.000s	1634.522us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	4.000s	1634.522us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	4.000s	1634.522us	2	2	100.00
sec_cm_bus_integrity				25	25	100.00
	rom_ctrl_tl_intg_err	31.000s	1895.984us	25	25	100.00
sec_cm_bus_local_esc				2	22	9.09
	rom_ctrl_corrupt_sig_fatal_chk	2187.000s	1000000.000us	0	20	0.00
	rom_ctrl_kmac_err_chk	4.000s	385.163us	2	2	100.00
sec_cm_mux_mubi				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2187.000s	1000000.000us	0	20	0.00
sec_cm_mux_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2187.000s	1000000.000us	0	20	0.00
sec_cm_ctrl_redun				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2187.000s	1000000.000us	0	20	0.00
sec_cm_ctrl_mem_integrity				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	10.000s	1096.882us	5	5	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	120.000s	753.456us	5	5	100.00

17/20 passed

85.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				17	20	85.00
	rom_ctrl_stress_all_with_rand_reset	71.000s	22318.699us	17	20	85.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				6 test runs
	rom_ctrl_corrupt_sig_fatal_chk	89206937709831775193703877452025781239808037159771612850541189657682968445206	98	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	37538894340852853362397490059190187479111418332620593775788014125560433308736	99	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	43425691531244245139335756235507918703972847451779543076452184077982295716414	88	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	97146231475500105774826222466017675090392690712360206074620220249920091570101	101	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	107890851099567408001523083940388117993869819781986419941055138744635670124509	98	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	94559615666795921872721559715236388371232268665900243164913247596036534140799	87	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles.				4 test runs
	rom_ctrl_corrupt_sig_fatal_chk	104377540083941835202915429604859373497222236548631734920678823250019938903292	88	UVM_INFO @ 65149016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	90656266176579754558154056548326145148465976695897352480937311818853155398656	88	UVM_INFO @ 180652314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	72582352894463078109034793822073183161885828118126025708650617323359315874902	87	UVM_INFO @ 61544066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	114331423795221899367750327557280260334656449925838884632341118144072272667577	90	UVM_INFO @ 26311176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:278) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow)				4 test runs
	rom_ctrl_corrupt_sig_fatal_chk	69253008609707583796938897834525962610301902047948839260899041117959311768113	88	UVM_INFO @ 10461758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	25631086381526635877699649016209249772096029268043445284553003398564652386241	87	UVM_INFO @ 2878542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	67774059038607561826053409927601983176718400129625046391652376739434371023291	89	UVM_INFO @ 25368484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	59375946726677604475306105994565468929042222342609477632537025658864887371949	88	UVM_INFO @ 13055724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:148) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)				3 test runs
	rom_ctrl_corrupt_sig_fatal_chk	82080897955387048148011337448403472768531755963112032209903787591981905261207	88	UVM_INFO @ 26972962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	34078784989831773320056387009301401710335587821055251402034441407173778905171	90	UVM_INFO @ 58587900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	70246265316849297072615836806230091342387423768597605884664437673575607347134	87	UVM_INFO @ 10449505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:*				3 test runs
	rom_ctrl_stress_all_with_rand_reset	46086271393960169780773382444987653637893622701485295569982479005274275101287	91	UVM_INFO @ 328159037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	8418034223459912253046406423575338901653862836880927115182013342631971111383	90	UVM_INFO @ 114619648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	101487012699092703318896003890695459211587060198185016829982108579928998060745	95	UVM_INFO @ 2986452340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:295) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.compare_vif.is_waiting())				3 test runs
	rom_ctrl_corrupt_sig_fatal_chk	32040659390060045338134537390369478157356632574094538487058773300738139653871	87	UVM_INFO @ 7861917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	7388539492549127543816469884711144974497509270339634433663248694266213159514	88	UVM_INFO @ 6414167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	25475433711322326882456483502690680687385707818274287844019210360929575333134	88	UVM_INFO @ 9755298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [] vs [*])				2 test runs
	rom_ctrl_max_throughput_chk	10176832252377695690311583909201445472037622338474243106855911727223400890640	88	UVM_INFO @ 163601229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_max_throughput_chk	46625707830008859314090410283947325393478896195466296230201958694482009422933	88	UVM_INFO @ 2978137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---