Simulation Results

Simulation Results: rom_ctrl/64kb

07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
95.66 %

code
90.02 %

assert
97.67 %

func
99.29 %

block
87.87 %

line
86.71 %

branch
88.64 %

toggle
84.74 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		94.37%
V2S		66.10%
V3		95.00%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	6.000s	404.753us	2	2	100.00
csr_hw_reset				1	1	100.00
	rom_ctrl_csr_hw_reset	6.000s	110.534us	1	1	100.00
csr_rw				5	5	100.00
	rom_ctrl_csr_rw	4.000s	52.097us	5	5	100.00
csr_bit_bash				1	1	100.00
	rom_ctrl_csr_bit_bash	4.000s	310.184us	1	1	100.00
csr_aliasing				1	1	100.00
	rom_ctrl_csr_aliasing	3.000s	80.589us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	5.000s	63.393us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rom_ctrl_csr_rw	4.000s	52.097us	5	5	100.00
	rom_ctrl_csr_aliasing	3.000s	80.589us	1	1	100.00
mem_walk				1	1	100.00
	rom_ctrl_mem_walk	3.000s	67.971us	1	1	100.00
mem_partial_access				1	1	100.00
	rom_ctrl_mem_partial_access	2.000s	51.015us	1	1	100.00

67/71 passed

94.37 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				0	2	0.00
	rom_ctrl_max_throughput_chk	3.000s	9.248us	0	2	0.00
stress_all				18	20	90.00
	rom_ctrl_stress_all	260.000s	1000000.000us	18	20	90.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	6.000s	736.282us	2	2	100.00
alert_test				10	10	100.00
	rom_ctrl_alert_test	4.000s	51.029us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rom_ctrl_tl_errors	9.000s	896.228us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rom_ctrl_tl_errors	9.000s	896.228us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rom_ctrl_csr_hw_reset	6.000s	110.534us	1	1	100.00
	rom_ctrl_csr_rw	4.000s	52.097us	5	5	100.00
	rom_ctrl_csr_aliasing	3.000s	80.589us	1	1	100.00
	rom_ctrl_same_csr_outstanding	4.000s	70.015us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rom_ctrl_csr_hw_reset	6.000s	110.534us	1	1	100.00
	rom_ctrl_csr_rw	4.000s	52.097us	5	5	100.00
	rom_ctrl_csr_aliasing	3.000s	80.589us	1	1	100.00
	rom_ctrl_same_csr_outstanding	4.000s	70.015us	5	5	100.00

V2S

39/59 passed

66.10 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2159.000s	1000000.000us	0	20	0.00
passthru_mem_tl_intg_err				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	15.000s	4066.840us	5	5	100.00
tl_intg_err				30	30	100.00
	rom_ctrl_sec_cm	236.000s	4939.298us	5	5	100.00
	rom_ctrl_tl_intg_err	60.000s	223.444us	25	25	100.00
prim_fsm_check				5	5	100.00
	rom_ctrl_sec_cm	236.000s	4939.298us	5	5	100.00
prim_count_check				5	5	100.00
	rom_ctrl_sec_cm	236.000s	4939.298us	5	5	100.00
sec_cm_checker_ctr_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2159.000s	1000000.000us	0	20	0.00
sec_cm_checker_ctrl_flow_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2159.000s	1000000.000us	0	20	0.00
sec_cm_checker_fsm_local_esc				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2159.000s	1000000.000us	0	20	0.00
sec_cm_compare_ctrl_flow_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2159.000s	1000000.000us	0	20	0.00
sec_cm_compare_ctr_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2159.000s	1000000.000us	0	20	0.00
sec_cm_compare_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	236.000s	4939.298us	5	5	100.00
sec_cm_fsm_sparse				5	5	100.00
	rom_ctrl_sec_cm	236.000s	4939.298us	5	5	100.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	6.000s	404.753us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	6.000s	404.753us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	6.000s	404.753us	2	2	100.00
sec_cm_bus_integrity				25	25	100.00
	rom_ctrl_tl_intg_err	60.000s	223.444us	25	25	100.00
sec_cm_bus_local_esc				2	22	9.09
	rom_ctrl_corrupt_sig_fatal_chk	2159.000s	1000000.000us	0	20	0.00
	rom_ctrl_kmac_err_chk	6.000s	736.282us	2	2	100.00
sec_cm_mux_mubi				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2159.000s	1000000.000us	0	20	0.00
sec_cm_mux_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2159.000s	1000000.000us	0	20	0.00
sec_cm_ctrl_redun				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2159.000s	1000000.000us	0	20	0.00
sec_cm_ctrl_mem_integrity				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	15.000s	4066.840us	5	5	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	236.000s	4939.298us	5	5	100.00

19/20 passed

95.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				19	20	95.00
	rom_ctrl_stress_all_with_rand_reset	83.000s	5584.253us	19	20	95.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				15 test runs
	rom_ctrl_corrupt_sig_fatal_chk	722147578416752620874295004784343016090885310347434392674375585819178593401	88	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	50665737774047957091587471963257407933882186887882614866912013368455650863976	97	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	52378523637979487144493262192182164985831934507961896505964565698075241759857	90	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	74864149900330756632379662302980520526774990136835637815194791152419012605592	90	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	15670112939094762054701326305966447493379093693484307509583599147486014151714	87	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	101292893228122490736862533662571708487333248258615534714876446137599585077905	89	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	75745901847791620775157599125202234644918248480641333708219885378866261594971	88	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	34748048077710076433291597059883983125054070075052033120637783915210300794414	92	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all	43523282440346330782619829047062345538600592112684277500371063496824540903841	87	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	22237013562649866948618626732434428591153333881980695931119009143942458353305	97	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	73630074201119885372943719888449878543731850497503583784444360093766711089206	88	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	2016202526827878412874435029859484796694776553532427297807774825574569441145	92	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	46186401546599059209723012618778605483631922274297390269668201503847689644928	87	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	51359493218013068688090623540157191678915646926130180918374033186938155727412	89	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	21991525416853387565774953621505743146325938138598862428638178996726990797091	90	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles.				3 test runs
	rom_ctrl_corrupt_sig_fatal_chk	58370768022871834248820403348187892667516230685730833756881096260362119593743	90	UVM_INFO @ 21381293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	102200689418980271578598078742944222221996029408401261052369402358991196921671	88	UVM_INFO @ 154295310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	347274052477407872967319151339087360408212531296164314424483258647043653686	89	UVM_INFO @ 72929989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:295) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.compare_vif.is_waiting())				3 test runs
	rom_ctrl_corrupt_sig_fatal_chk	44317315936696865309004288444402159588072567705274644432850407986496822220957	87	UVM_INFO @ 21179112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	89759740043411149638517911753127756521334171455222376931746390953866721799835	88	UVM_INFO @ 663166456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	30535927329360551180547659002602209316409175888714723400405647261548167334535	88	UVM_INFO @ 8999111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [] vs [*])				2 test runs
	rom_ctrl_max_throughput_chk	110376888133927341724488275861407135518407451745793669132993785979365317923009	88	UVM_INFO @ 9247954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_max_throughput_chk	926550464191904804153439307031197564754613259799210062470515811399695212475	88	UVM_INFO @ 8000425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:*				1 test run
	rom_ctrl_stress_all_with_rand_reset	2964789202736916766863032271291327465765061771487697353821243026623721312050	91	UVM_INFO @ 988374624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] Expected alert (fatal) did not fire in * cycles.				1 test run
	rom_ctrl_stress_all	14960464222049567539772503062308331662567127473154558731556453726434241917294	87	UVM_INFO @ 664561773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---