Simulation Results: rstmgr

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.92 %
  • code
  • 99.56 %
  • assert
  • 98.72 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 99.90 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 1.790s 76.072us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.520s 65.074us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.290s 36.012us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.690s 81.558us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.650s 40.758us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.690s 98.770us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.290s 36.012us 5 5 100.00
rstmgr_csr_aliasing 1.650s 40.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 2.700s 201.504us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 1.530s 38.996us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.420s 47.731us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 8.440s 736.435us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 8.440s 736.435us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 8.440s 736.435us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 8.440s 736.435us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 34.220s 2960.710us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.390s 49.494us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 3.990s 96.004us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 3.990s 96.004us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.520s 65.074us 1 1 100.00
rstmgr_csr_rw 1.290s 36.012us 5 5 100.00
rstmgr_csr_aliasing 1.650s 40.758us 1 1 100.00
rstmgr_same_csr_outstanding 1.940s 73.070us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.520s 65.074us 1 1 100.00
rstmgr_csr_rw 1.290s 36.012us 5 5 100.00
rstmgr_csr_aliasing 1.650s 40.758us 1 1 100.00
rstmgr_same_csr_outstanding 1.940s 73.070us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rstmgr_sec_cm 71.120s 10483.725us 5 5 100.00
rstmgr_tl_intg_err 6.060s 653.177us 25 25 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 71.120s 10483.725us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 71.120s 10483.725us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
rstmgr_tl_intg_err 6.060s 653.177us 25 25 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.660s 54.837us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 24 25 96.00
rstmgr_leaf_rst_cnsty 6.820s 468.485us 24 25 96.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 3.620s 292.290us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 71.120s 10483.725us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.290s 36.012us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.290s 36.012us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* 1 test run
rstmgr_leaf_rst_cnsty 91899627006143982903644967572679724021958392440514972117821972131542504194874 103
UVM_INFO @ 158245839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---