Simulation Results

Simulation Results: rv_dm/use_dmi_interface

07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
91.91 %

code
83.25 %

assert
96.90 %

func
95.57 %

block
93.68 %

line
94.33 %

branch
82.87 %

toggle
75.45 %

FSM
80.36 %

Validation stages

V1		98.46%
V2		43.89%
V2S		94.00%
V3		10.00%
unmapped		0.00%

128/130 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	48.000s	419.492us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	44.000s	610.233us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	50.000s	266.318us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	57.000s	5379.047us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	49.000s	462.415us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	45.000s	10715.509us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	81.000s	16377.376us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	117.000s	129360.417us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	107.000s	37611.602us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	37.000s	764.229us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	44.000s	226.175us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	43.000s	201.618us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	42.000s	201.846us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	48.000s	132.046us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	45.000s	311.465us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	33.000s	137.821us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	46.000s	972.711us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	37.000s	764.229us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	52.000s	101.761us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	52.000s	1202.644us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	43.000s	201.618us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	40.000s	148.363us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	40.000s	100.330us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	49.000s	400.280us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	58.000s	10581.741us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	79.000s	4967.253us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	45.000s	85.205us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	79.000s	4967.253us	1	1	100.00
	rv_dm_csr_rw	49.000s	400.280us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	42.000s	72.464us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	39.000s	35.742us	1	1	100.00

79/180 passed

43.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	48.000s	419.492us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	35.000s	304.754us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	39.000s	191.817us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	41.000s	551.477us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	49.000s	1482.424us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	86.000s	17780.202us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	49.000s	916.053us	0	20	0.00
bad_sba				1	20	5.00
	rv_dm_bad_sba_tl_access	71.000s	19461.199us	1	20	5.00
sba_autoincrement				4	20	20.00
	rv_dm_autoincr_sba_tl_access	102.000s	28923.314us	4	20	20.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	49.000s	105.377us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	42.000s	2328.889us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	47.000s	386.629us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	45.000s	65.118us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	44.000s	7109.441us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	121.000s	17710.208us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	45.000s	78.881us	1	1	100.00
stress_all				1	20	5.00
	rv_dm_stress_all	10800.000s	0.000us	1	20	5.00
alert_test				10	10	100.00
	rv_dm_alert_test	47.000s	121.778us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	56.000s	160.130us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	56.000s	160.130us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	79.000s	4967.253us	1	1	100.00
	rv_dm_csr_hw_reset	40.000s	100.330us	1	1	100.00
	rv_dm_csr_rw	49.000s	400.280us	5	5	100.00
	rv_dm_same_csr_outstanding	52.000s	331.577us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	79.000s	4967.253us	1	1	100.00
	rv_dm_csr_hw_reset	40.000s	100.330us	1	1	100.00
	rv_dm_csr_rw	49.000s	400.280us	5	5	100.00
	rv_dm_same_csr_outstanding	52.000s	331.577us	5	5	100.00

V2S

47/50 passed

94.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	44.000s	2179.447us	5	5	100.00
	rv_dm_tl_intg_err	59.000s	2773.444us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	59.000s	2773.444us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	42.000s	2328.889us	2	2	100.00
	rv_dm_debug_disabled	50.000s	127.598us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	42.000s	2328.889us	2	2	100.00
	rv_dm_debug_disabled	50.000s	127.598us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	48.000s	419.492us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				7	10	70.00
	rv_dm_buffered_enable	50.000s	245.214us	7	10	70.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	44.000s	279.816us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	44.000s	279.816us	4	4	100.00
sec_cm_exec_ctrl_mubi				7	10	70.00
	rv_dm_buffered_enable	50.000s	245.214us	7	10	70.00

2/20 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				2	20	10.00
	rv_dm_stress_all_with_rand_reset	92.000s	4224.038us	2	20	10.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	309.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				38 test runs
	rv_dm_sba_tl_access	114599367335370403429308815267747627814494449593710117554031300759212000279140	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23878
	rv_dm_bad_sba_tl_access	32019647074998680035432470391611706286267666740972405235607682360005944767766	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23900
	rv_dm_sba_tl_access	114167471298262538202320432928575924317245441400482492228153757547935042677186	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23850
	rv_dm_bad_sba_tl_access	1833333236515860236255993044411388863309741464021395236255913474401601266446	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24031
	rv_dm_sba_tl_access	78831450608002788713094768761778942977446855826515205234655109562575492275489	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10264
	rv_dm_bad_sba_tl_access	106454574524323907418993174959713646117606263275699063379074650446561773525106	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23806
	rv_dm_sba_tl_access	101590970686810861942711650891881477966826680093089764926239320596559740801665	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23852
	rv_dm_sba_tl_access	76415683421428092000121394037515181221646270561329435602959047993437381855726	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_bad_sba_tl_access	70126549184660115777035775151186458992131375882257890319928290928326603648037	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_autoincr_sba_tl_access	61094191910263606079257374261220955637917708989358760450056229954634404335146	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @16078
	rv_dm_sba_tl_access	40352162386033629672818276563137487552543743612908299035164389067114446210624	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23906
	rv_dm_bad_sba_tl_access	36404824350497187726493450183563675219753335860064231252819263912791032972500	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23865
	rv_dm_sba_tl_access	78191849208462939000323827057971702335851093470732834042028140926834890188981	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23879
	rv_dm_bad_sba_tl_access	57760523161854756794823665847111962767786126818725322884911635193185029677275	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24226
	rv_dm_sba_tl_access	34952126450343341116555271123360277121116044178345317163015994856771325794216	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10061
	rv_dm_bad_sba_tl_access	16835012213570389120301781907934575927260604039282577916542170790302743980094	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23741
	rv_dm_autoincr_sba_tl_access	95989652157200711032215352311976721894739151942523393396457119672650303712951	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23853
	rv_dm_sba_tl_access	88423757029600151296930704208761462262270600290393684017149701087805002297950	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23806
	rv_dm_sba_tl_access	104213653876278816055219463080947390932313195825775631170998631434590355963259	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23783
	rv_dm_bad_sba_tl_access	25634388081299562853905057682915018152944674441703550942714474540697927712626	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23784
	rv_dm_autoincr_sba_tl_access	24489775988950833017042978392879794076777228642003015543058201764023089919921	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23853
	rv_dm_sba_tl_access	22985184254332588167020786387048631534313454632247590848215965860711678196029	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23807
	rv_dm_bad_sba_tl_access	58869568211889345141698413737730023463199058659235986247820262057365208750476	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23781
	rv_dm_sba_tl_access	114528831119815929542504907971531593107866053240226232946941722749865432754459	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23873
	rv_dm_sba_tl_access	71045280588517248313479841812426553653362568714467124181739082876443557025539	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23903
	rv_dm_bad_sba_tl_access	14561622418412756257832938907126548773854214536495795496905133773949409065755	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24435
	rv_dm_autoincr_sba_tl_access	5307536928986247877710234017691285040404679408963440564031958524134480778206	129	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24097
	rv_dm_sba_tl_access	69732894964174317362473134518723799911132447771060154234705732585089418477064	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23806
	rv_dm_sba_tl_access	11443904915725556058458034825319222275279454658482979655175203756400593063916	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10263
	rv_dm_autoincr_sba_tl_access	66070173963776328862263307464246964310954171920041719540724158639949077036053	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23878
	rv_dm_sba_tl_access	85194325099125569311144052759541182976215907869423101476373174962055578689176	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10261
	rv_dm_autoincr_sba_tl_access	51639436895779050898863418385788756607614263225205175750613689909033814663021	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23783
	rv_dm_sba_tl_access	23081131275733188488813513900753130434998113104338478264801761438285243884939	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_sba_tl_access	107283557296465456508910554885599533406899823484629085330555281904693124338190	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23860
	rv_dm_sba_tl_access	95178371944529365295348860782302003394190505701665900205620019937756536186727	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_bad_sba_tl_access	95602106986529573585356933529874152688044324069545260344403907191975329887023	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23910
	rv_dm_autoincr_sba_tl_access	101863437922238589520514642086948740441229274461826357420316294641719843520848	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24097
	rv_dm_sba_tl_access	62666415673297586108524372401552237169145762414270687466047551708171077512889	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				37 test runs
	rv_dm_delayed_resp_sba_tl_access	9663147969528609725510158471285330456900880988906498670764023445166119265529	107	UVM_INFO @ 259863968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	25511437923947536625935908746349576641866930614278615960192296093970119729871	107	UVM_INFO @ 67016975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	86551778642980445945367104982370276363742305387015828061587462131477848153392	107	UVM_INFO @ 233189489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	30568961004903782924267265745877063274788942009446913026507204405839557570334	107	UVM_INFO @ 2049887582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	72050756322528564543706451471701685384395653157714029148115484974711228614078	107	UVM_INFO @ 167714167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	39289295332576762349985079989469562403468871736693204136365390518062377048328	107	UVM_INFO @ 85916913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	21569907599647108451077903907676820638494393657199838703911125355088076427581	107	UVM_INFO @ 71197169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	11184898417506642304875982966259963710594328617833386499285668221233026529888	107	UVM_INFO @ 165529719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	105548132836878858852837125424566139881695932188669378779308375763305211875804	107	UVM_INFO @ 130529620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	25001890632591653382391195607745880655974777005796766269383431904011360946279	107	UVM_INFO @ 99804244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	34267118092728059345792474626890006368085204709216819354732243319868807701493	107	UVM_INFO @ 232477968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	83223431799069152184161144008743178052576047560186298573811043369545934911276	107	UVM_INFO @ 198223329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	47928439322688392062049056368135302445005191396771723140859266735792265803245	107	UVM_INFO @ 180146292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	94257279423676571621299024339042606895437432480872023901321035843763189874301	107	UVM_INFO @ 451132627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	101698783058981080265016595581856416217884048739743110082285654305328578864669	107	UVM_INFO @ 57395057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	112268532033665969875777189072425898647051295915362764501471017833282805209170	107	UVM_INFO @ 1515747386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	110133304830988824200615174184277581697291177490686985685010346785607486098865	107	UVM_INFO @ 226195566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	88894384448391475164926734475205819667523161828474910486971842125966162900815	107	UVM_INFO @ 134912514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	20519042680532240794822409303283254567079910513660076480404867983049270177191	107	UVM_INFO @ 88252064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	4145707984910134242345352861059981193799605657443761774699890455185914307295	107	UVM_INFO @ 150572216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	87297625467789306875359337415768888314307722720128268582674504119400237084472	107	UVM_INFO @ 564686077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	48217659712191930622852036874531996045817927541420105247620878434132883353883	107	UVM_INFO @ 87204909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	55470721592767368312816656166805753344997091344772559906796869466552032239424	107	UVM_INFO @ 427923189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	37822377523689154010487342409397652364014796938446741200031919017022225415285	107	UVM_INFO @ 142568538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	104440356221512256201277389068056681757659229214066728915815664698135371319847	107	UVM_INFO @ 343128456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	107179513315675417365011901758303672722918728475145690711689431902183784875882	107	UVM_INFO @ 72178347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	89803022993596746327726347654499928124400876553179641061655951520763471947941	107	UVM_INFO @ 916053374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	4959689606411480853104684520862069457471522767163140956937944110393309604426	107	UVM_INFO @ 61199924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	94625574800683740373627134769153340636418280632364789862231986734264267379924	107	UVM_INFO @ 298867174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	71984988436733423890499041542306459575625221199791280257725615364509132875644	107	UVM_INFO @ 169713818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	42203912847576071809021541255973144756733327697768243413045811049868728858515	107	UVM_INFO @ 195435333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	76410306807901165709518713049778967020761739986171782228732971923148513854672	107	UVM_INFO @ 57898359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	46313959976319583977289284540230648200503031380696493883590850174517495393846	107	UVM_INFO @ 382161349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	109928273804296739446317867797352199307893086835336303938996928008348271976604	107	UVM_INFO @ 382102875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	87467993506745025501829884109235120625697959397854320119786666205454854089974	107	UVM_INFO @ 58977848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	105892921612834167166923551006048049501445468211262245453971904070746537742104	107	UVM_INFO @ 194990083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	43662150497749013173907676222294876148376392287324211571254391086864394365505	107	UVM_INFO @ 155280044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				16 test runs
	rv_dm_mem_tl_access_resuming	47912662314121698917578698296693626946905958032217928336861124883949261726575	87	UVM_INFO @ 201845644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	90070311515841198672230037887620550516543201150784682423630974813348228111115	89	UVM_INFO @ 473592879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	82677921311028157011587281567878112239543145801372864304588130967778065712263	87	UVM_INFO @ 192090777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	27619786971574475670105493187085698280602683428667540172302004468396395417870	88	UVM_INFO @ 347033953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	32122271643419640387434644469818535133274098705406111967487784981127723647330	101	UVM_INFO @ 426214460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	32226876727809277278735043980135520167433351041347534053778615009663084532028	101	UVM_INFO @ 370943474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	103034919579423918711929647966588085715092375798505961480879463851197569146146	93	UVM_INFO @ 632420825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	36649300428629401809245373218099193622248755578759824870271415273077858307018	90	UVM_INFO @ 1541370538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	106677355736972032372714015438865396109923061034725869133919952099994931792739	114	UVM_INFO @ 828534383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	63532451382426905949621096848995984593279960096509184082919564974260412628586	92	UVM_INFO @ 246814890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	32982003769432667921187390878888349490125747505836673129659559583770773707980	90	UVM_INFO @ 816066160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	43958243976641034430382904824714663452333680681467648119902389319121450431410	89	UVM_INFO @ 256771332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	43686136520520807149555057961741829719975478893823603860342358520290782264567	89	UVM_INFO @ 877078840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	30834639014354127593687160592326944406615228391280440605144759642209843741010	97	UVM_INFO @ 231471573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	45568806358055762388279692141350162410783728150206906814980400111990632897629	91	UVM_INFO @ 2389125907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	64612235096416751235071194477558758248155269311026372291794696311443103240808	91	UVM_INFO @ 106775964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				14 test runs
	rv_dm_hart_unavail	17280036491933159591934670327059608067568204656272925327428625745485983032968	87	UVM_INFO @ 119487352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	97834545996404486457068231963781949475319309753704488682946409920266280577764	162	UVM_INFO @ 4224038384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	60108109291553797456852317135724001373137082375094177122670334063742760971042	87	UVM_INFO @ 443355271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	66462672531298451497693316703882299275968739624313402123298908772102879514876	90	UVM_INFO @ 895018096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	40407573499699528328428746641378699978645372271675485128917259497278525831492	87	UVM_INFO @ 65118224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	260825804327228999588570649781451265016917121973087545272209558976668370162	87	UVM_INFO @ 39431527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	33265922140898240911414657714489126606728707028514374902570572332037598369642	87	UVM_INFO @ 228251760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	94721316608539889715546839144217966492972266057195877253977193014864631207969	94	UVM_INFO @ 2027603278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	76728916792978505907174703290059329695220439714922954211258789256083778815425	91	UVM_INFO @ 162028553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	55347441551441424047007328501637203800415867406768792109629907820639236574868	98	UVM_INFO @ 3187560308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	104025243434714476377396492164682256857930898987503546461616967133078593006082	90	UVM_INFO @ 466590728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	39885696848130197059116773438064984216784676148042429890377659857020868759457	90	UVM_INFO @ 2601447082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	4122441010653667025795166790672366507359634334686944983959912695083271559398	89	UVM_INFO @ 1284822204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	35516605597538156113167708304816186566652222871043344841437851214228022948043	107	UVM_INFO @ 1453118053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				6 test runs
	rv_dm_scanmode	33843280450070662515472182524949679403046768555152947746201697336988307962715	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	96722538795257464411452819374733297345158528512175360723274399041801109058583	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	59923814630141790421097583559279571739203680008761255711838099470159264109771	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	51777135045995739050439401046309312064199925802745201905291691699935316998691	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	110303435813712815060484533736453948433883742725797036545728701496392400634169	93	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	47905588970754459330246330180054859968300820898192335918536480569747711732791	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				5 test runs
	rv_dm_jtag_dmi_debug_disabled	23419818078621016823953891164209413807835793624070002807398038815711216356302	87	UVM_INFO @ 105376738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	53252306719173397121433378489410681897034171026413278704972681074933876225527	87	UVM_INFO @ 124243423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	98199176623855879408757441028099928599514212136151515062506808291727167987480	89	UVM_INFO @ 372361640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	54866322265418179195411634638317747818500458284153271953874604320456611162384	98	UVM_INFO @ 460652737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	40188447643558094006146787136326638357390918469308748441170957907970173802043	91	UVM_INFO @ 90359768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				5 test runs
	rv_dm_stress_all_with_rand_reset	104594491150102526620579944406411896208631440084998500446771037862425078387975	114	UVM_INFO @ 537397959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	90276510291638061448020642078034499181736862230908706188940770644049599818041	112	UVM_INFO @ 851447015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	99170949555052740821469765082038714183264202331471004338517962859548266552002	108	UVM_INFO @ 867849657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	102274021463558113161179816765838082553639516440316968185980599072459210749584	113	UVM_INFO @ 2000838244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	50899029453764957720555218331409372674998474921930930233096428878624899300483	101	UVM_INFO @ 551909793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				3 test runs
	rv_dm_buffered_enable	58516461329218876621750421422781640621560248324543712373154943130598906135869	93	UVM_INFO @ 84491423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	75462011768112752618842834392048961755219798420845786242488901838091423057828	89	UVM_INFO @ 171406883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	53977679134394842269891585977743166097334631439816273278660665135838186419595	93	UVM_INFO @ 293313036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	rv_dm_stress_all	110254441498928302594810305113159958925706651895186064216837135075973526091382	None