Simulation Results: rv_timer

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.18 %
  • code
  • 90.45 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
85.04%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 837.559us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 17.267us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 6.000s 27.491us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 565.398us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 37.180us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 55.743us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 6.000s 27.491us 5 5 100.00
rv_timer_csr_aliasing 2.000s 37.180us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 20 5.00
rv_timer_random_reset 2.000s 537.240us 1 20 5.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 3291.168us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 333.000s 1166071.909us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 333.000s 1166071.909us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 6.000s 9155.619us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 31.789us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 1.000s 35.729us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 4.000s 402.634us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 4.000s 402.634us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 17.267us 1 1 100.00
rv_timer_csr_rw 6.000s 27.491us 5 5 100.00
rv_timer_csr_aliasing 2.000s 37.180us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 18.463us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 17.267us 1 1 100.00
rv_timer_csr_rw 6.000s 27.491us 5 5 100.00
rv_timer_csr_aliasing 2.000s 37.180us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 18.463us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.000s 41.420us 5 5 100.00
rv_timer_tl_intg_err 2.000s 288.091us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 288.091us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 3.000s 1657.391us 2 10 20.00
max_value 0 10 0.00
rv_timer_max 2.000s 479.706us 0 10 0.00
stress_all_with_rand_reset 14 20 70.00
rv_timer_stress_all_with_rand_reset 61.000s 19645.479us 14 20 70.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 27 test runs
rv_timer_random_reset 68894730306720942968184790708119200930330234324023764197701558399708341334202 84
UVM_INFO @ 537240100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 15207516421301344152736027895745791523763279553201124587905865509113066318982 85
UVM_INFO @ 125124710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 22675034233064350626911507170631891241271220037455423476461857773934394241843 84
UVM_INFO @ 62911293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 62860269725646020520208707565136061662956449102391526751393486367188471787062 86
UVM_INFO @ 80773261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 53876001100895404045663278214324962044729530395532251416215627192402252390614 84
UVM_INFO @ 177590222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 72894954618146755402706762953532098170794280429520888831866101019578117996077 86
UVM_INFO @ 67152966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 107664018856232927507136431243549229734254244165773902947750275123237916172025 86
UVM_INFO @ 233139188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 44522773860511542910686729932461068552687296403363361245738538734218211813261 84
UVM_INFO @ 440705616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 65235538178269000891596738964394741162756750590469985913853707830841045832104 84
UVM_INFO @ 549499233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 58634531150776620762447178656666538781126865880946128260365897563338654175167 84
UVM_INFO @ 63944159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 79505808726930524277222551172266038030164974669683867370808909741970206402023 84
UVM_INFO @ 397976480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 51575656318115904589395019090194410782794112203925520624739253526845825278715 87
UVM_INFO @ 1657391074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 20662994672816365228364509579740275080175536235674397067755894244871239183946 84
UVM_INFO @ 242140456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 30442867657230989964132759098045362595251631250531280283753530600813520204916 85
UVM_INFO @ 70104284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 3903408405569067593758051124636125099068895502602220613983552721940638837016 84
UVM_INFO @ 534509279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 96091856592742309077494326579708749637328500155985506040344743440212401464909 84
UVM_INFO @ 164313844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 113253155233807608833837019099319785374701961033082905480383071448693247357302 84
UVM_INFO @ 260006914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 21686370918525685361132814222259467057212363345125337991290440633954625580651 84
UVM_INFO @ 78254042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 65102957892413225311206908769969776376597581539305300951650824597680888874093 86
UVM_INFO @ 150867293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 99624700617565963572398635462167788274679228005202879848061949571120395582274 84
UVM_INFO @ 188377963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 88883593733957448893609627624384644684499031332692921832675760347033330623509 84
UVM_INFO @ 76934411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 55846869809247741460848032751474759317109464377494712995948145646266640329986 84
UVM_INFO @ 1135289344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 101889564822650464820895504885230132062370741624097157759928710778057182996988 86
UVM_INFO @ 870874614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 47241512427632474755949128780490587261932715219329744409076144536758946733818 84
UVM_INFO @ 149755503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 75251243470242399601948223223263200851929898701159896416235148951149356531322 84
UVM_INFO @ 1241248947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 17328338746205721212270622101362996212639997897647628733019061594412423037808 85
UVM_INFO @ 241452104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 3801942233309077193591147151190268990329716814351653116992471474414099017 84
UVM_INFO @ 221008582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 8 test runs
rv_timer_max 96515810278600013657784994412295226243577404711370861913605003380492821703753 84
UVM_INFO @ 424285402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 61540943553761505450321257297253972444371379922221124489128465816214284302221 84
UVM_INFO @ 51881371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 71918444838476434124232965929620056398006729656499621501061385527357595971628 85
UVM_INFO @ 479706148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 7794969820470755965064219939354221980632700234397567633210994151331245244973 84
UVM_INFO @ 125127222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 36981308458746603220275393668572233297937835065735139190660349906547885093541 84
UVM_INFO @ 46283595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 94265579731529345268795286689491551865032417433767315020821204337678875965654 84
UVM_INFO @ 46024507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 76888961824013926204243251141334457723658435668201774485684974337204511846373 84
UVM_INFO @ 88268767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 33781549236645347551687807506654789339069459784004121817918101486835285051675 84
UVM_INFO @ 182292800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 3 test runs
rv_timer_stress_all_with_rand_reset 107855688975705965397723954582470604846433483952593444039017749666524995487797 456
UVM_INFO @ 12359037560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 42596820062146313619282787021015505298822060802764215466245091160778096000537 164
UVM_INFO @ 1358499976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 30709110245761970754800704337249262168984446636483721829811301651677761445716 375
UVM_INFO @ 21009186254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
rv_timer_stress_all_with_rand_reset 62561880648879968000940160838080785248899458384980916774591745207058796032185 474
UVM_INFO @ 5286754413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 112950884184397871019638477616353959745758799432572875960889694108950627391884 199
UVM_INFO @ 4046730654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 34167458246617324652755063267585485735300407076425106527233670375103392650668 88
UVM_INFO @ 2662616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 2 test runs
rv_timer_max 61593482610762194308666035604899927708703602126812922179800462518938229223843 84
UVM_INFO @ 43756796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 63956285966470813969972605497870901325824298415213572924370245619994366994575 84
UVM_INFO @ 44884600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---