Simulation Results: spi_host

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.82 %
  • code
  • 91.30 %
  • assert
  • 96.41 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.90%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 70.000s 2601.682us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 46.635us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 18.259us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 5.000s 254.644us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 24.532us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 29.712us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 18.259us 5 5 100.00
spi_host_csr_aliasing 2.000s 24.532us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 14.715us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 64.379us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 49.053us 10 10 100.00
error_event_intr 29 30 96.67
spi_host_overflow_underflow 4.000s 296.081us 10 10 100.00
spi_host_error_cmd 2.000s 25.603us 10 10 100.00
spi_host_event 434.000s 89231.515us 9 10 90.00
clock_rate 10 10 100.00
spi_host_speed 6.000s 1176.499us 10 10 100.00
speed 10 10 100.00
spi_host_speed 6.000s 1176.499us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 6.000s 1176.499us 10 10 100.00
upper_range_clkdiv 4 5 80.00
spi_host_upper_range_clkdiv 152.000s 12256.166us 4 5 80.00
sw_reset 10 10 100.00
spi_host_sw_reset 66.000s 2329.425us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 26.184us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 6.000s 1176.499us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 6.000s 1176.499us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 70.000s 2601.682us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 70.000s 2601.682us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 24.000s 1304.398us 10 10 100.00
spien 10 10 100.00
spi_host_spien 62.000s 8941.299us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 359.000s 132739.161us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 44.000s 9545.301us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 4.000s 296.081us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 28.825us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 15.510us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 212.991us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 212.991us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 46.635us 1 1 100.00
spi_host_csr_rw 2.000s 18.259us 5 5 100.00
spi_host_csr_aliasing 2.000s 24.532us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 102.779us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 46.635us 1 1 100.00
spi_host_csr_rw 2.000s 18.259us 5 5 100.00
spi_host_csr_aliasing 2.000s 24.532us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 102.779us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 224.317us 25 25 100.00
spi_host_sec_cm 2.000s 76.357us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 224.317us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_upper_range_clkdiv 31690143270691018555381774576596482116386987258583571602753104347864657690696 152
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_host_event_vseq.sv:45) [spi_host_event_vseq] Check failed txqd == spi_host_ctrl_reg.tx_watermark - i (* [*] vs * [*]) 1 test run
spi_host_event 554129760010536628852248070119717325869609778116072807501425700373806425289 101
UVM_INFO @ 7132517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---