| V1 |
|
98.11% |
| V2 |
|
98.86% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| ac_range_check_smoke | 20 | 20 | 100.00 | |||
| ac_range_check_smoke | 57.000s | 11786.026us | 20 | 20 | 100.00 | |
| ac_range_check_smoke_racl | 19 | 20 | 95.00 | |||
| ac_range_check_smoke_racl | 74.000s | 2584.809us | 19 | 20 | 95.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| ac_range_check_csr_hw_reset | 3.000s | 179.223us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| ac_range_check_csr_rw | 3.000s | 196.175us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| ac_range_check_csr_bit_bash | 31.000s | 6409.767us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| ac_range_check_csr_aliasing | 45.000s | 1259.066us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| ac_range_check_csr_mem_rw_with_rand_reset | 3.000s | 27.330us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| ac_range_check_csr_rw | 3.000s | 196.175us | 5 | 5 | 100.00 | |
| ac_range_check_csr_aliasing | 45.000s | 1259.066us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| ac_range_check_lock_range | 20 | 20 | 100.00 | |||
| ac_range_check_lock_range | 4.000s | 117.103us | 20 | 20 | 100.00 | |
| ac_range_bypass_enable | 1 | 1 | 100.00 | |||
| ac_range_check_bypass | 72.000s | 30521.888us | 1 | 1 | 100.00 | |
| stress_all | 9 | 10 | 90.00 | |||
| ac_range_check_stress_all | 218.000s | 7245.704us | 9 | 10 | 90.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| ac_range_check_alert_test | 32.000s | 13.929us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| ac_range_check_intr_test | 2.000s | 26.668us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| ac_range_check_tl_errors | 6.000s | 161.728us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| ac_range_check_tl_errors | 6.000s | 161.728us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| ac_range_check_csr_hw_reset | 3.000s | 179.223us | 1 | 1 | 100.00 | |
| ac_range_check_csr_rw | 3.000s | 196.175us | 5 | 5 | 100.00 | |
| ac_range_check_csr_aliasing | 45.000s | 1259.066us | 1 | 1 | 100.00 | |
| ac_range_check_same_csr_outstanding | 6.000s | 2761.555us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| ac_range_check_csr_hw_reset | 3.000s | 179.223us | 1 | 1 | 100.00 | |
| ac_range_check_csr_rw | 3.000s | 196.175us | 5 | 5 | 100.00 | |
| ac_range_check_csr_aliasing | 45.000s | 1259.066us | 1 | 1 | 100.00 | |
| ac_range_check_same_csr_outstanding | 6.000s | 2761.555us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| ac_range_check_shadow_reg_errors | 26.000s | 1193.243us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| ac_range_check_shadow_reg_errors | 26.000s | 1193.243us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| ac_range_check_shadow_reg_errors | 26.000s | 1193.243us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| ac_range_check_shadow_reg_errors | 26.000s | 1193.243us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| ac_range_check_shadow_reg_errors_with_csr_rw | 137.000s | 9720.050us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| ac_range_check_sec_cm | 2.000s | 40.934us | 5 | 5 | 100.00 | |
| ac_range_check_tl_intg_err | 14.000s | 360.676us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 10 | 10 | 100.00 | |||
| ac_range_check_stress_all_with_rand_reset | 353.000s | 816.393us | 10 | 10 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 20 | 20 | 100.00 | |||
| ac_range_check_smoke_high_threshold | 57.000s | 2004.876us | 20 | 20 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (ac_range_check_scoreboard.sv:166) [scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo. | 1 test run | |||
| ac_range_check_stress_all | 16466961752159205474241664216612458855076391583393155174157364753034889007420 | 17479 |
UVM_INFO @ 100332011227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (ac_range_check_scoreboard.sv:373) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state | 1 test run | |||
| ac_range_check_smoke_racl | 71062341441279711604749728322667369150178123283546062318962202709069903573476 | 4076 |
UVM_INFO @ 684804550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|