| V1 |
|
100.00% |
| V2 |
|
89.94% |
| V2S |
|
94.63% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.670s | 9981.993us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 11.830s | 1578.542us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 15.010s | 1141.530us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 754.080s | 92761.019us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 328.900s | 28974.929us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 15.050s | 147.446us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 15.010s | 1141.530us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 328.900s | 28974.929us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 405.430s | 6927.847us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 92.420s | 6050.934us | 50 | 50 | 100.00 | |
| entropy | 22 | 25 | 88.00 | |||
| alert_handler_entropy | 3600.146s | 0.000us | 22 | 25 | 88.00 | |
| sig_int_fail | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 86.070s | 1640.175us | 49 | 50 | 98.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.670s | 9981.993us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 72.380s | 1573.103us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 100.660s | 3509.385us | 50 | 50 | 100.00 | |
| ping_timeout | 33 | 50 | 66.00 | |||
| alert_handler_ping_timeout | 604.220s | 17388.169us | 33 | 50 | 66.00 | |
| lpg | 91 | 100 | 91.00 | |||
| alert_handler_lpg | 3600.404s | 0.000us | 43 | 50 | 86.00 | |
| alert_handler_lpg_stub_clk | 3600.138s | 0.000us | 48 | 50 | 96.00 | |
| stress_all | 49 | 50 | 98.00 | |||
| alert_handler_stress_all | 5371.430s | 329155.994us | 49 | 50 | 98.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 34.760s | 707.239us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 6.610s | 135.787us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.430s | 28.652us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 31.120s | 1446.439us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 31.120s | 1446.439us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 11.830s | 1578.542us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 15.010s | 1141.530us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 328.900s | 28974.929us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 69.310s | 3071.423us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 11.830s | 1578.542us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 15.010s | 1141.530us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 328.900s | 28974.929us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 69.310s | 3071.423us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 558.650s | 40202.469us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 558.650s | 40202.469us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 558.650s | 40202.469us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 558.650s | 40202.469us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1458.290s | 34526.752us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 67.810s | 1166.703us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 109.310s | 2524.256us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 109.310s | 2524.256us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 558.650s | 40202.469us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.670s | 9981.993us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.670s | 9981.993us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.670s | 9981.993us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 67.670s | 9981.993us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 86.070s | 1640.175us | 49 | 50 | 98.00 | |
| sec_cm_lpg_intersig_mubi | 43 | 50 | 86.00 | |||
| alert_handler_lpg | 3600.404s | 0.000us | 43 | 50 | 86.00 | |
| sec_cm_esc_intersig_diff | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 86.070s | 1640.175us | 49 | 50 | 98.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 22 | 25 | 88.00 | |||
| alert_handler_entropy | 3600.146s | 0.000us | 22 | 25 | 88.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 22 | 25 | 88.00 | |||
| alert_handler_entropy | 3600.146s | 0.000us | 22 | 25 | 88.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 67.810s | 1166.703us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 67.810s | 1166.703us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 67.810s | 1166.703us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 67.810s | 1166.703us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 67.810s | 1166.703us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 67.810s | 1166.703us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 67.810s | 1166.703us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 67.810s | 1166.703us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 67.810s | 1166.703us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 5 | 10 | 50.00 | |||
| alert_handler_stress_all_with_rand_reset | 318.400s | 3347.254us | 5 | 10 | 50.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 1318677640537279216370112733998796334993708378937119684727358283193684728996 | 212 |
UVM_INFO @ 667450296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 50903394358051728853111670251930686972628134850329107828930027210088369007830 | 236 |
UVM_INFO @ 3255757385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 51481315476675876011458922703768588262826294416425627772122392290866436058238 | 202 |
UVM_INFO @ 141497137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 52475479982005559052469155753251894279314397078947385044210353895844608355639 | 226 |
UVM_INFO @ 859315899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 11725201205254427012381333884367083285722339763246075093737886074285277720352 | 132 |
UVM_INFO @ 1022702837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 20119414172851792870724524008352835700060811624706242960851863890321334283269 | 172 |
UVM_INFO @ 460648424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 97853194623755221734686728009124063075747776820150437204274542240848642005164 | 174 |
UVM_INFO @ 102494196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 111757266393576939621921628007543931398471070837638676865352461641792010626899 | 174 |
UVM_INFO @ 487315803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 4259841449934936172858317147983840710865320781133125883410460256397923630077 | 232 |
UVM_INFO @ 707238902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 82784799022689458918900636937652734491335675122087574719642804261645477587766 | 148 |
UVM_INFO @ 124936582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 29682677156780449665725790447241568910454913040731469486763556806670080369011 | 232 |
UVM_INFO @ 1973481278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 20886698240897200448313805503118999587222478770425924808184812234670036692113 | 132 |
UVM_INFO @ 375525035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 82912992049334716822283638994343050944230540281328927012922527213131006324421 | 214 |
UVM_INFO @ 110290300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 1420761785006984168142978574687364101479907564654892582571122360877732246003 | 206 |
UVM_INFO @ 109869778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 22763057926735499860659333480056258643219036415976670949184002670331520279279 | 216 |
UVM_INFO @ 238288405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 91480197959328649237116019811254372635035505185134850185361322420731736011622 | 232 |
UVM_INFO @ 200215138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 27613470027082948077120643742072159561645524225003172980129671203430761630352 | 232 |
UVM_INFO @ 1409086852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 57228535618190656861995916557939809254884765929879498197555652041305544250117 | 210 |
UVM_INFO @ 350977591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 85368128908683682313999621264883842135298109654603045940516516997366647846806 | 236 |
UVM_INFO @ 458335697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 88354429607568778292019149804473461978470612952462684621092255039095302950852 | 190 |
UVM_INFO @ 213175085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 14 test runs | |||
| alert_handler_ping_timeout | 97830015415151323257262297843832525827274466989019764063762023400339811379125 | 104 |
UVM_INFO @ 32793364765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 73220216737662110846584930432437078810469925357644791183505127301324077200061 | 96 |
UVM_INFO @ 6948450440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 79351826168322897253384085883023297971062646456699194091450364955868235706699 | 105 |
UVM_INFO @ 10296814616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 108571871322889999201948046455720798556883046996551402278497585372489709938190 | 116 |
UVM_INFO @ 5615414359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 40956084637905250955971677649512747896554210091693527397848093548645158433184 | 96 |
UVM_INFO @ 1995064930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 106161104568943026940529901131165098914268896149987111407537777630596286784204 | 99 |
UVM_INFO @ 1724607393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 89891290850544242182613608249320248200381403895208062666106727086275701172660 | 108 |
UVM_INFO @ 2387830478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 76388986082258822790308106577655636993056839244176140691330168775815758424894 | 135 |
UVM_INFO @ 33459654495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 46108048406539680219641789833112362191808847952682445219484401495457109691923 | 105 |
UVM_INFO @ 2435534800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 56331097116500382546103446281275457425302309789783480957785045050843824469267 | 86 |
UVM_INFO @ 48413196283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 71971582200639711014217081842925289126336609066284573959497494018687068982588 | 93 |
UVM_INFO @ 4686194164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 84429817494026004168017031077649339804670056101848050257679614845767932628928 | 141 |
UVM_INFO @ 19262296227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 83950830443347306971097365845002459223834165650043030441463212166820157006702 | 90 |
UVM_INFO @ 1221923256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 74892538180315205157618251549957459707650669432363411008217933886622516408672 | 99 |
UVM_INFO @ 1969436675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 10 test runs | |||
| alert_handler_entropy | 2188430848144387484461819721186339747800006575605272258671249053654445864492 | None | ||
| alert_handler_lpg | 46429054181869366633543133301037417495708848741940635112873548806956112905742 | None | ||
| alert_handler_lpg | 23194962685134417890600740351821235464623542911445328422354948690930589919208 | None | ||
| alert_handler_entropy | 101759290295544463562740345106875292089901877548660123272030678041404962578104 | None | ||
| alert_handler_entropy | 59869475714836173860884509588945233731040334581978038726695663441192803405280 | None | ||
| alert_handler_lpg | 49212506893692019716821954572426491740320406894146349510259175670951978082070 | None | ||
| alert_handler_lpg | 63654592663825793847227834550232197381803724176438389104750648476125904468442 | None | ||
| alert_handler_lpg | 1989127703870258024193124541501802342455053596556260853910247610561772976210 | None | ||
| alert_handler_lpg_stub_clk | 26344170150473722844764920623896435503423572636295486108760314737279024137954 | None | ||
| alert_handler_lpg | 100442221315797099393932884465734235247440306837827333404405389053964139670999 | None | ||
| UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 5 test runs | |||
| alert_handler_stress_all_with_rand_reset | 89842608432078037015507156830440397988470246676484899848794031328777009696141 | 89 |
UVM_INFO @ 413156451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 79619320578974144799019842510376600725995035819774623856760440690535782279406 | 142 |
UVM_INFO @ 2340667950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 62609223587346166851457997768955388313287150627970924655801271907050217894005 | 89 |
UVM_INFO @ 116949090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 10117761645828085787824225207748979734337108043585053721719237143561399618883 | 141 |
UVM_INFO @ 4009387550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 25423807369090014474808975713797694898914594353841426791854387793283463174381 | 93 |
UVM_INFO @ 463941686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:604) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 4 test runs | |||
| alert_handler_ping_timeout | 6845806148651538119499841993664915816045305581270624406965965400811278305394 | 86 |
UVM_INFO @ 129823818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 104717330764760858898762219637774903158526415494599356410707563082128112533859 | 86 |
UVM_INFO @ 280122486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_ping_timeout | 108695765444942926259569150703409687256069536290021106499190637758696569241953 | 86 |
UVM_INFO @ 28266439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 54289253470215467988177671129358099286944362944485513380505303914015214000738 | 86 |
UVM_INFO @ 661664973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:341) [scoreboard] Check failed cycle_cnt <= exp_cycle (* [*] vs * [*]) | 1 test run | |||
| alert_handler_stress_all | 9455939987855694187106240440065441977942274679674508832289296564971325481442 | 326 |
UVM_INFO @ 19108972587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| alert_handler_lpg_stub_clk | 114154613957532105732172378113339156860686251031718635671363604087048579656919 | 86 |
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) | 1 test run | |||
| alert_handler_sig_int_fail | 10926035014449956913944371228093886085554152556286581379048220173057144907810 | 93 |
UVM_INFO @ 292934151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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