| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| aon_timer_smoke | 3.000s | 546.186us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_hw_reset | 22.000s | 724.846us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| aon_timer_csr_rw | 11.000s | 340.769us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aon_timer_csr_bit_bash | 27.000s | 7296.829us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aon_timer_csr_aliasing | 23.000s | 329.655us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 15.000s | 370.396us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| aon_timer_csr_rw | 11.000s | 340.769us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 23.000s | 329.655us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| aon_timer_mem_walk | 2.000s | 324.002us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| aon_timer_mem_partial_access | 2.000s | 351.188us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 15 | 15 | 100.00 | |||
| aon_timer_prescaler | 74.000s | 61958.570us | 15 | 15 | 100.00 | |
| jump | 5 | 5 | 100.00 | |||
| aon_timer_jump | 4.000s | 696.615us | 5 | 5 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| aon_timer_stress_all | 219.000s | 155060.594us | 15 | 15 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| aon_timer_alert_test | 28.000s | 429.496us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| aon_timer_intr_test | 4.000s | 370.061us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| aon_timer_tl_errors | 4.000s | 569.557us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| aon_timer_tl_errors | 4.000s | 569.557us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| aon_timer_csr_hw_reset | 22.000s | 724.846us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 11.000s | 340.769us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 23.000s | 329.655us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 7.000s | 2756.605us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| aon_timer_csr_hw_reset | 22.000s | 724.846us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 11.000s | 340.769us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 23.000s | 329.655us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 7.000s | 2756.605us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| aon_timer_sec_cm | 20.000s | 8500.939us | 5 | 5 | 100.00 | |
| aon_timer_tl_intg_err | 19.000s | 7984.526us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| aon_timer_tl_intg_err | 19.000s | 7984.526us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_max_thold | 2.000s | 509.347us | 5 | 5 | 100.00 | |
| min_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_min_thold | 3.000s | 683.299us | 5 | 5 | 100.00 | |
| wkup_count_hi_cdc | 5 | 5 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 11.000s | 3150.640us | 5 | 5 | 100.00 | |
| custom_intr | 10 | 10 | 100.00 | |||
| aon_timer_custom_intr | 8.000s | 480.382us | 10 | 10 | 100.00 | |
| alternating_on_off | 5 | 5 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 46.000s | 4260.935us | 5 | 5 | 100.00 | |
| stress_all_with_rand_reset | 15 | 15 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 30.000s | 18154.876us | 15 | 15 | 100.00 | |