Simulation Results

Simulation Results: clkmgr

14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
78.38 %

code
70.05 %

assert
90.29 %

func
74.80 %

line
82.42 %

branch
87.53 %

cond
80.31 %

toggle
100.00 %

FSM
0.00 %

Validation stages

V1		69.57%
V2		70.09%
V2S		30.48%
V3		0.00%

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.230s	86.996us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.260s	20.432us	1	1	100.00
csr_rw				2	5	40.00
	clkmgr_csr_rw	1.910s	78.354us	2	5	40.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	3.480s	186.947us	0	1	0.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	2.130s	80.462us	1	1	100.00
csr_mem_rw_with_rand_reset				2	5	40.00
	clkmgr_csr_mem_rw_with_rand_reset	2.650s	103.828us	2	5	40.00
regwen_csr_and_corresponding_lockable_csr				3	6	50.00
	clkmgr_csr_rw	1.910s	78.354us	2	5	40.00
	clkmgr_csr_aliasing	2.130s	80.462us	1	1	100.00

82/117 passed

70.09 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.570s	42.842us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	2.690s	105.763us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.910s	73.913us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.230s	86.996us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.260s	21.563us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.010s	6.385us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.260s	21.563us	0	10	0.00
stress_all				2	10	20.00
	clkmgr_stress_all	11.120s	717.157us	2	10	20.00
alert_test				10	10	100.00
	clkmgr_alert_test	3.540s	205.194us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	12.690s	731.531us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	12.690s	731.531us	25	25	100.00
tl_d_outstanding_access				5	12	41.67
	clkmgr_csr_hw_reset	1.260s	20.432us	1	1	100.00
	clkmgr_csr_rw	1.910s	78.354us	2	5	40.00
	clkmgr_csr_aliasing	2.130s	80.462us	1	1	100.00
	clkmgr_same_csr_outstanding	1.810s	57.176us	1	5	20.00
tl_d_partial_access				5	12	41.67
	clkmgr_csr_hw_reset	1.260s	20.432us	1	1	100.00
	clkmgr_csr_rw	1.910s	78.354us	2	5	40.00
	clkmgr_csr_aliasing	2.130s	80.462us	1	1	100.00
	clkmgr_same_csr_outstanding	1.810s	57.176us	1	5	20.00

V2S

32/105 passed

30.48 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				1	30	3.33
	clkmgr_sec_cm	136.050s	10005.035us	1	5	20.00
	clkmgr_tl_intg_err	1.740s	35.232us	0	25	0.00
shadow_reg_update_error				19	20	95.00
	clkmgr_shadow_reg_errors	2004.570s	200000.000us	19	20	95.00
shadow_reg_read_clear_staged_value				19	20	95.00
	clkmgr_shadow_reg_errors	2004.570s	200000.000us	19	20	95.00
shadow_reg_storage_error				19	20	95.00
	clkmgr_shadow_reg_errors	2004.570s	200000.000us	19	20	95.00
shadowed_reset_glitch				19	20	95.00
	clkmgr_shadow_reg_errors	2004.570s	200000.000us	19	20	95.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	2.200s	127.111us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	1.740s	35.232us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.260s	21.563us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.010s	6.385us	0	10	0.00
sec_cm_meas_config_shadow				19	20	95.00
	clkmgr_shadow_reg_errors	2004.570s	200000.000us	19	20	95.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	3.690s	202.459us	10	10	100.00
sec_cm_jitter_config_mubi				2	5	40.00
	clkmgr_csr_rw	1.910s	78.354us	2	5	40.00
sec_cm_idle_ctr_redun				1	5	20.00
	clkmgr_sec_cm	136.050s	10005.035us	1	5	20.00
sec_cm_meas_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.910s	78.354us	2	5	40.00
sec_cm_clk_ctrl_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.910s	78.354us	2	5	40.00
prim_count_check				1	5	20.00
	clkmgr_sec_cm	136.050s	10005.035us	1	5	20.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.200s	11.770us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	99.260s	7894.892us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				29 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	13419008221233823432476978352073703931223938490955898467302167307500373159794	81	UVM_INFO @ 10848970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	40804092277508210631787954212877035949678900880164697508937453574624310929799	82	UVM_INFO @ 15415508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	68014250157351865760744641745708028151640185022652554380376039855786736714905	92	UVM_INFO @ 21537672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	66019654586182293705830496498131876486641843621622827912749012112503565025982	82	UVM_INFO @ 2397219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	82922707914722118311631625061554395576430657187076268168690273974731334045832	81	UVM_INFO @ 5940639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	1461818823670497961481496155663852681187960804199768432156351072632486898067	81	UVM_INFO @ 2913806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	10286028876932821564417728454180187476711965707898417213792976134692134595480	81	UVM_INFO @ 14183449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	61862835213272942440947715079357329066982038619903333940336021251040915682666	96	UVM_INFO @ 21782716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	101463238353792303353301781912463434647083291587689452983995008858563269113098	82	UVM_INFO @ 4539952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	81161403591869155091052455249480337088584522906705941981427267706286942932461	81	UVM_INFO @ 4400784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	82157046834566463589875577560442916546070822251341441597519043120863689406741	99	UVM_INFO @ 14295231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	75635276202359753856605408568409636043560004878139203568765234586839981713759	81	UVM_INFO @ 19872376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	108555960148715349010453214623833975920744174684359502579238400308565474885579	91	UVM_INFO @ 2978030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	77429698506026838337891163866139717613233101978012696947788575726625953207183	81	UVM_INFO @ 6625683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	3854265391415269037145948977653839410864833273986989847346019097449397039055	81	UVM_INFO @ 2913646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	9774738709727300700920358128871633802057298562479458381160273139034309194173	81	UVM_INFO @ 127111432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	86113623551097296233669967032851901907755545931411445090417974112553139509778	81	UVM_INFO @ 11327971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	84092941349424244897210877735648073437605879172371281394528554952792898509576	99	UVM_INFO @ 18861513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	38072211738022794153739578496365054837660723535507967220882965906290195565462	81	UVM_INFO @ 19559922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	68640840596976563475313087792870563553179598341397981246208066308858044601994	100	UVM_INFO @ 29814027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	20934478473970878062933148170800914191335662823228087627867985098160314345140	81	UVM_INFO @ 4970704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	5299825966246926790250931900551053138201836083053453964215678639370151464869	91	UVM_INFO @ 2449276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	61176041543707930382408282517401388476698496719828932628865432014963275166943	81	UVM_INFO @ 63425821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	78481525836803049886249970767246810958815924987791409336385628056550141904606	81	UVM_INFO @ 3025054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	33547469260159236039809868202033910521154645881593349836074617799469382629451	95	UVM_INFO @ 9647996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	72636086691364924859050017444906621663116889543870883928739788445123646856559	81	UVM_INFO @ 3421531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	96595178674575080334109709343534007647450774128209743695687742079266745944298	129	UVM_INFO @ 35232458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	50098606736922711465750259384937490449904448553064843818959095327091924809396	81	UVM_INFO @ 2290706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	11689486542734306025666161188877301106957135038701219424070334160448368863452	81	UVM_INFO @ 2093220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				23 test runs
	clkmgr_frequency_timeout	53424720108828024444605439262297147590190169212022841675088744976948799762013	83	UVM_INFO @ 2000199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	16430302401836376429388914574550722997526184044237831803593221731688889047271	100	UVM_INFO @ 66857360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	10743074647489052823711747241068971679732946190212060440296216680754945415610	84	UVM_INFO @ 4074801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	93091668937001799641559990390881542830282544981662827229368852312034747038311	313	UVM_INFO @ 7894891952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	72795667217257272395884673301531108848081350536113405166284311971302144715166	84	UVM_INFO @ 4651183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	78340708686422836319161757774010536870169883745585875968660956259235077823947	85	UVM_INFO @ 5441948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	44310265879136649751214862437075608327733596758267072439132497896287827448690	83	UVM_INFO @ 25142117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	110803868108380742507452979856471689191975077385282377616072443325848737505903	83	UVM_INFO @ 4291075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	71111870721671472813745709887211758509482998005329673533283249694410816894409	163	UVM_INFO @ 51222604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	2787127835172273433675836673156824828449502747045060826084109024019224874640	83	UVM_INFO @ 3483114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	70416960056426403995208662003533640216572358232115005792037600754217243318520	85	UVM_INFO @ 48983378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	64649517186934462307158535436846404866581446092828611661635625707608486224804	119	UVM_INFO @ 22556996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	26544230453449723296137923890400879738956291587451646093584662187993539962990	84	UVM_INFO @ 6308652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	993274540064750472400937797934519094135148134656594869711286732408658982900	156	UVM_INFO @ 49744660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	47236316723430946967692257963229732649007228879058454854643064317220069106904	84	UVM_INFO @ 2706676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	17057321048554178869692140809550846969752172208682869877719911395091530840899	85	UVM_INFO @ 3355058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	53782055304254906336210413559680357123810946828275899030114271314087023581095	84	UVM_INFO @ 2689053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	79872188766762213597434353054671437515072404616215150707887603904164515810048	223	UVM_INFO @ 717157123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	91030159385321005045005547797250907597611681671347631517690284728677370026266	84	UVM_INFO @ 6385389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	39444488151678634729843051052747646992135676785324953048331355205696484765005	135	UVM_INFO @ 1002481910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	15264153806237300883092696311632913567118320833044724198188198184000256824807	155	UVM_INFO @ 51110102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	31889658982710494399064488057147699526221987207072988324788781025274522186506	83	UVM_INFO @ 4133199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	91048543310076136601248617090055592887567277425758391370830511830711754909138	85	UVM_INFO @ 5964991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				22 test runs
	clkmgr_tl_intg_err	99323074791939851572946442867054344936655209553673412559730409397311765860869	81	UVM_INFO @ 1526741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	67036663566795239603373044653923793023680832054462307256729125620475889917218	81	UVM_INFO @ 6192715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	105808607988356318526631730600707772261263518707806778093263214904792628524674	91	UVM_INFO @ 4839159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	12265900345246296404047884227061382747148221137885870996810932440709288312702	81	UVM_INFO @ 3059909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	32078979803221929324532811462283249916690830867354578103164157713307148223628	81	UVM_INFO @ 2262558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	83778732678856780082303543152399096721739177729118220785571239426797978072888	82	UVM_INFO @ 12929773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	9196263391206883101849938540463869547130206794786373137641719816465618814309	82	UVM_INFO @ 13777074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	78817502598144056654093255790746468721682186292057118776543266093320083413885	81	UVM_INFO @ 11480786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	49917741853162733927010917012092542850430258176242147511675561468650705440413	88	UVM_INFO @ 21491116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	90604120429746662404500808139028266610298536042059515820181432226324216938181	84	UVM_INFO @ 6803259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	109229729802330422351587633556908598635329169137753000580061086440897148644744	81	UVM_INFO @ 3986739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	52671383784241144245134519568307750216803221714068524814511122924069354783552	81	UVM_INFO @ 3161592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	10316821558545818572670418955962585171166844882902614999611484403920619912276	81	UVM_INFO @ 3322184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	24074106820849548354539578989745320498035121257130923746528247769075854342935	84	UVM_INFO @ 4422732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	24048045319594034484319192964858580587184556174566789049893449878471576420378	81	UVM_INFO @ 4142219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	30178154495331421484267940573982383806962660258208748113074560329310553401960	81	UVM_INFO @ 1349666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	95675828194378567021275833121435274883601777526263707955053317821715377902522	81	UVM_INFO @ 10571506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	115418229377963091809068041183384421480699688141177377503192671611776557458899	99	UVM_INFO @ 8774728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	48314603420727124561307058839205864090975936430218606573411750987733989803492	81	UVM_INFO @ 3997224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	90748999697795360915350311884895288315022470674949028700978571698147836695357	88	UVM_INFO @ 4701453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	47217363590321592098344806443214173393118588071457830416485561869047287802129	81	UVM_INFO @ 4070013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	49961424567292635014244704405311546937391536193583582147113031866678628593377	99	UVM_INFO @ 8064389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				15 test runs
	clkmgr_frequency	103740618872346940186411083839146435479996523957557176627494296070719799714437	82	UVM_INFO @ 21563182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	33144751406640925451598302394159177219106882512269540637063665924109046244486	83	UVM_INFO @ 22252082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	61294589728755446785782054082070145449560480824345390626178704187634898467641	83	UVM_INFO @ 14418615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	51439018822217661854621349152535635752079711092498104944150952656950944993161	81	UVM_INFO @ 4048724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	38783590950256936017116220818178431324860271741362629108117381395860879092084	81	UVM_INFO @ 5349770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	98127435296721546396780939209795424232100190021896958173834523343833663984021	128	UVM_INFO @ 2125783920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	68267071671867121078660320640233871003179768044961316708345419008877691317662	81	UVM_INFO @ 13804311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	1613737265015245325186100151526523174687396311040024968123819422641175954421	82	UVM_INFO @ 22756432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	51846015781856734300512035167915350579150566386427893351903735520667867615483	160	UVM_INFO @ 58945061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	32103746266358492964039277843697152283497383168974638299152748793363213334457	82	UVM_INFO @ 16577797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	51729315707730547000784605565093900447130314437931188688984499925174292475435	81	UVM_INFO @ 7534148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	12888873274601910827730364976025858091784936155246516286768332748111484644978	132	UVM_INFO @ 64304349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	45994459394808076081306229186764832002118554194651376674294498933062442113739	84	UVM_INFO @ 10506847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	21981048685575963833099939126163539784122489683379433867968958776519489120675	82	UVM_INFO @ 6589275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	17887230201817992628806545485683997149658658325490390929808246428808154445963	82	UVM_INFO @ 8084297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				5 test runs
	clkmgr_regwen	7665626491438265543119766413504120641827576980930839031105770108046638139896	80	UVM_INFO @ 2138604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	25200231186407169574662876208702788877354651506380979461275562016902614305336	80	UVM_INFO @ 7363760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	47534531786082707489907322190333467533593808984988456268021174769080846882758	80	UVM_INFO @ 5939140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	93609287285921341577056841011516467527958502554914360679235189663176971437519	80	UVM_INFO @ 9332463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	23197270225022418351395043961753667458910931192603819752574039877011543977227	80	UVM_INFO @ 7650868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				4 test runs
	clkmgr_same_csr_outstanding	109499172384692097751959580647184705360975794523781765477911737572804547852489	81	UVM_INFO @ 31465873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	105221027858452394682141396445717233733411786360741649080393748367583212465336	81	UVM_INFO @ 6713250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	55682346177867262475407574700200212644994218830585977086533488503264517740667	81	UVM_INFO @ 27992208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	86206633467598210265018052329785105083560506861603983467385145251169124633472	81	UVM_INFO @ 2724267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				4 test runs
	clkmgr_regwen	70141585813574339920803981673424136846122247082324966087624839679570765370472	80	UVM_INFO @ 12995050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	83595834392369561835470061520898911951505397943260084751651781744148235693523	80	UVM_INFO @ 10291053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	10663940741945664305337373985358773501841457463528862537694834102454100698144	80	UVM_INFO @ 11769979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	110686578993548473552161536043451875230350406650558390420181514520745459309525	80	UVM_INFO @ 2914790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1087) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				3 test runs
	clkmgr_sec_cm	84904115841564712383519963747937800810325144243959663110242637787070795284001	215	UVM_INFO @ 10311201228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	68006708233320186869777508086067075704614436192853429286971447429347932786323	130	UVM_INFO @ 10435235351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	87383374130602382997576633984386208717948658854596877509007968814344850152982	86	UVM_INFO @ 10005034528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	7626955145404116577516321059319239398105457648260090097702540819100808637541	81	UVM_INFO @ 186946919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en				1 test run
	clkmgr_regwen	83235003862607197614248187493509638377345157433809609074837015615536830089899	80	UVM_INFO @ 6057929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				1 test run
	clkmgr_sec_cm	104841210426525228552005948303221382893155985261442567069891670147607313640533	96	UVM_INFO @ 22228310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	clkmgr_shadow_reg_errors	30859708169511467087110489482760457228019530377045011100320560883310932680139	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---