Simulation Results: csrng

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.51 %
  • code
  • 96.17 %
  • assert
  • 96.51 %
  • func
  • 90.86 %
  • block
  • 98.49 %
  • line
  • 99.50 %
  • branch
  • 96.30 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.16%
V2S
98.83%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 6.000s 257.638us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 33.000s 20.955us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 32.000s 16.713us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 49.000s 338.401us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 35.000s 101.025us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 34.000s 172.626us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 32.000s 16.713us 5 5 100.00
csrng_csr_aliasing 35.000s 101.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
alerts 500 500 100.00
csrng_alert 64.000s 5697.527us 500 500 100.00
err 500 500 100.00
csrng_err 31.000s 42.128us 500 500 100.00
cmds 1 25 4.00
csrng_cmds 44.000s 1825.619us 1 25 4.00
life cycle 1 25 4.00
csrng_cmds 44.000s 1825.619us 1 25 4.00
stress_all 25 25 100.00
csrng_stress_all 1141.000s 76313.712us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 27.000s 68.425us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 33.000s 21.527us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 13.000s 468.016us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 13.000s 468.016us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 33.000s 20.955us 1 1 100.00
csrng_csr_rw 32.000s 16.713us 5 5 100.00
csrng_csr_aliasing 35.000s 101.025us 1 1 100.00
csrng_same_csr_outstanding 21.000s 48.246us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 33.000s 20.955us 1 1 100.00
csrng_csr_rw 32.000s 16.713us 5 5 100.00
csrng_csr_aliasing 35.000s 101.025us 1 1 100.00
csrng_same_csr_outstanding 21.000s 48.246us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 9.000s 254.350us 5 5 100.00
csrng_tl_intg_err 22.000s 2114.845us 25 25 100.00
sec_cm_config_regwen 15 30 50.00
csrng_regwen 20.000s 16.077us 10 25 40.00
csrng_csr_rw 32.000s 16.713us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 64.000s 5697.527us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 1141.000s 76313.712us 25 25 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
csrng_sec_cm 9.000s 254.350us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
csrng_sec_cm 9.000s 254.350us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
csrng_sec_cm 9.000s 254.350us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
csrng_sec_cm 9.000s 254.350us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
csrng_sec_cm 9.000s 254.350us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 64.000s 5697.527us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 1141.000s 76313.712us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 64.000s 5697.527us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 22.000s 2114.845us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
csrng_sec_cm 9.000s 254.350us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
csrng_sec_cm 9.000s 254.350us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 32.000s 98.938us 200 200 100.00
csrng_err 31.000s 42.128us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:667) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 23 test runs
csrng_cmds 84296110341551554468505441634014598406659792920285364698997164240585404482660 100
UVM_INFO @ 104563922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 54624655291239372094795935720359232045845674198037458794091254928192457575432 100
UVM_INFO @ 942016352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 19625799871785438703723967904729367173394459614452416177086086298919309164192 100
UVM_INFO @ 14954116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 79238002094640572868377394703363936844965509996777623952284224622689664865002 100
UVM_INFO @ 55954787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 99985255854607519090523779552800537268470616063013840964084856901868186343887 100
UVM_INFO @ 134440442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 65330340073822970468076392364464332007342992484825981208782711975142785574697 100
UVM_INFO @ 527956271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 3328787999592752970006777159588748694257315627395798583031155543112506486620 100
UVM_INFO @ 156052235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 76897449460311507646679238222331866209587857657560221472078712641278398844466 100
UVM_INFO @ 51812324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103547005862307001152022887614542010337025976572174654965392319460043621697182 100
UVM_INFO @ 133910946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 89791673949889754188168488610848498478369760118300770909213594523345035254031 100
UVM_INFO @ 1585971515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 18004043755935641394264083303780221056695955699503578042166785696117030733181 110
UVM_INFO @ 252718584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 73643696463863284759831122769227180229699303641247592060840044000368965852820 100
UVM_INFO @ 23083946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 56154302901433872015329346180788837137579067273051545648262553849603144243746 100
UVM_INFO @ 84492901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 5386428363459319617923760999701975654463310669796994845101761873623434328129 100
UVM_INFO @ 103457187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 10332513260632042179583808008400505875620172309876473702940775608039786355163 100
UVM_INFO @ 956784640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 67571699385058676798865715247393079115355383043643325995505256475316305483012 110
UVM_INFO @ 177330373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 73446081851815978235232462818610000871646992287694090787305836803960305665455 100
UVM_INFO @ 127670165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 91569308959236140764924188728112254296586643486149666244053848674743654047166 100
UVM_INFO @ 211156439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 19741190415525602192591545652075751348434712402308964319258282870544837159851 109
UVM_INFO @ 95037374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 49323809547746322296794043262485947090477193742710431992745188349742040883163 100
UVM_INFO @ 33948505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 69612028838269389430157430538643967654748333687966595997198465519395907647017 100
UVM_INFO @ 64512370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 13930211238606254683215805008364129332348473832228194155115859644670080022046 100
UVM_INFO @ 86976503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 92891014785836637954482634802111054737463329042685136690771228231993405677534 100
UVM_INFO @ 295112119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 10 test runs
csrng_regwen 11421975717707499549827624446285714747967707823508198626220538815144202110621 99
UVM_INFO @ 7251631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 29518190473739041471114381833816482080025748303805540601673267826832096717743 99
UVM_INFO @ 10600202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 7168403058647881951573785911129920534858814356759620501359384644779984605486 99
UVM_INFO @ 23452423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 79582282679065878890671142481182725693017717148850008239957405875899995561012 99
UVM_INFO @ 12181296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 61879903751302708056219506125466615084753258675618676020087491309611801838088 99
UVM_INFO @ 7476219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 1686262748068494982738108830144969951748588323158412321582583971184498936166 99
UVM_INFO @ 6182466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 102959994469387387702116494967054488730101293588524766155257463545400888108602 99
UVM_INFO @ 1677428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 71625251946125140372393741190521225492659219642865554763617543209638500363990 99
UVM_INFO @ 11506659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 69093877044373450788351059827569167231913711141953643221521521175786444078522 99
UVM_INFO @ 26840292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 45463611205943313830358885185166154622795774569343363808108115117443371345020 99
UVM_INFO @ 3687122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 5 test runs
csrng_regwen 5709343941986837066433677845633599944484654316502126361161029128726481435164 99
UVM_INFO @ 8799683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 115592292464638149654490839099759354706147227069839308454414133427701941043473 99
UVM_INFO @ 10163793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 71834148442309290387001073670871297060704459287911096978673533053206344375873 99
UVM_INFO @ 5841050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 78840509256756664494895052011562618115815168346226222050918878315904838312182 99
UVM_INFO @ 6052956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 63727770522443957272840164781136219781188834536087259960915612941454272383718 99
UVM_INFO @ 5055131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 5 test runs
csrng_stress_all_with_rand_reset 74612637131844935112081655313990848290627261371593320184705544039645441080435 None
csrng_stress_all_with_rand_reset 5140592664697177754080810870345176988443073143884075773930605775956020106049 None
csrng_stress_all_with_rand_reset 57292135201594509618347321572924406660183381159577158252564230269166286858522 None
csrng_stress_all_with_rand_reset 56848427581236391182506345191854811685608413847404082262793129382725450650869 None
csrng_stress_all_with_rand_reset 43745639028747647564149617520788539079405949148521015766695577794631814078396 None
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 3 test runs
csrng_stress_all_with_rand_reset 13584977161316621705291451096120824073825383938510251890179276208645448625148 148
UVM_INFO @ 13203297525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 106619917277892091297491546910779348408303321723842443055180377481029385026331 105
UVM_INFO @ 7488342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 18492701346833890168565166339303263491742410339134232401255273600236660167981 104
UVM_INFO @ 31081086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:173) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 27438325567191670498775087057628383087943087378719913470842592684836750766979 112
UVM_INFO @ 55093190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:636) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 94708318027936802274009678295659446243154113027199672653738255015256321495756 109
UVM_INFO @ 73086075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---