| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| unmapped |
|
96.77% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_smoke | 25 | 25 | 100.00 | |||
| dma_memory_smoke | 8.000s | 1418.182us | 25 | 25 | 100.00 | |
| dma_handshake_smoke | 25 | 25 | 100.00 | |||
| dma_handshake_smoke | 9.000s | 1365.964us | 25 | 25 | 100.00 | |
| dma_generic_smoke | 50 | 50 | 100.00 | |||
| dma_generic_smoke | 9.000s | 429.311us | 50 | 50 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 107.961us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| dma_csr_rw | 2.000s | 66.367us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| dma_csr_bit_bash | 13.000s | 4112.512us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| dma_csr_aliasing | 9.000s | 1950.765us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| dma_csr_mem_rw_with_rand_reset | 2.000s | 28.656us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| dma_csr_rw | 2.000s | 66.367us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 9.000s | 1950.765us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_region_lock | 5 | 5 | 100.00 | |||
| dma_memory_region_lock | 122.000s | 7621.776us | 5 | 5 | 100.00 | |
| dma_memory_tl_error | 3 | 3 | 100.00 | |||
| dma_memory_stress | 413.000s | 64049.501us | 3 | 3 | 100.00 | |
| dma_handshake_tl_error | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 590.000s | 95700.562us | 3 | 3 | 100.00 | |
| dma_handshake_stress | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 590.000s | 95700.562us | 3 | 3 | 100.00 | |
| dma_memory_stress | 3 | 3 | 100.00 | |||
| dma_memory_stress | 413.000s | 64049.501us | 3 | 3 | 100.00 | |
| dma_generic_stress | 5 | 5 | 100.00 | |||
| dma_generic_stress | 672.000s | 194410.920us | 5 | 5 | 100.00 | |
| dma_handshake_mem_buffer_overflow | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 590.000s | 95700.562us | 3 | 3 | 100.00 | |
| dma_abort | 5 | 5 | 100.00 | |||
| dma_abort | 16.000s | 4835.445us | 5 | 5 | 100.00 | |
| dma_stress_all | 3 | 3 | 100.00 | |||
| dma_stress_all | 219.000s | 58086.315us | 3 | 3 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| dma_alert_test | 2.000s | 24.672us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| dma_intr_test | 2.000s | 24.650us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| dma_tl_errors | 9.000s | 89.634us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| dma_tl_errors | 9.000s | 89.634us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 107.961us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 66.367us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 9.000s | 1950.765us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 3.000s | 200.371us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| dma_csr_hw_reset | 2.000s | 107.961us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 66.367us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 9.000s | 1950.765us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 3.000s | 200.371us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_illegal_addr_range | 13 | 13 | 100.00 | |||
| dma_mem_enabled | 23.000s | 366.856us | 5 | 5 | 100.00 | |
| dma_generic_stress | 672.000s | 194410.920us | 5 | 5 | 100.00 | |
| dma_handshake_stress | 590.000s | 95700.562us | 3 | 3 | 100.00 | |
| dma_config_lock | 15 | 15 | 100.00 | |||
| dma_config_lock | 14.000s | 3976.973us | 15 | 15 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| dma_tl_intg_err | 8.000s | 411.827us | 25 | 25 | 100.00 | |
| dma_sec_cm | 6.000s | 12.471us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 30 | 31 | 96.77 | |||
| dma_short_transfer | 213.000s | 19777.084us | 25 | 25 | 100.00 | |
| dma_longer_transfer | 6.000s | 1504.880us | 5 | 5 | 100.00 | |
| dma_stress_all_with_rand_reset | 22.000s | 2726.581us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| dma_stress_all_with_rand_reset | 5467434105007967213247566105838352852135397110032503100707879274390430537888 | 129 |
UVM_INFO @ 2726580536ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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