Simulation Results: edn/edn0

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.35 %
  • code
  • 95.28 %
  • assert
  • 98.89 %
  • func
  • 58.88 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.01%
V2S
100.00%
V3
76.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 2.000s 22.534us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 20.061us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 50.726us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 141.845us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 21.157us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 48.437us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 50.726us 5 5 100.00
edn_csr_aliasing 2.000s 21.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 86.000s 8767.784us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 86.000s 8767.784us 100 100 100.00
genbits 100 100 100.00
edn_genbits 86.000s 8767.784us 100 100 100.00
interrupts 20 20 100.00
edn_intr 2.000s 69.448us 20 20 100.00
alerts 200 200 100.00
edn_alert 12.000s 31.243us 200 200 100.00
errs 100 100 100.00
edn_err 11.000s 21.459us 100 100 100.00
disable 94 100 94.00
edn_disable 6.000s 35.839us 50 50 100.00
edn_disable_auto_req_mode 7.000s 33.283us 44 50 88.00
stress_all 30 30 100.00
edn_stress_all 8.000s 313.431us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 16.382us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 71.755us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.000s 1178.655us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.000s 1178.655us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.000s 20.061us 1 1 100.00
edn_csr_rw 2.000s 50.726us 5 5 100.00
edn_csr_aliasing 2.000s 21.157us 1 1 100.00
edn_same_csr_outstanding 2.000s 37.299us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.000s 20.061us 1 1 100.00
edn_csr_rw 2.000s 50.726us 5 5 100.00
edn_csr_aliasing 2.000s 21.157us 1 1 100.00
edn_same_csr_outstanding 2.000s 37.299us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 9.000s 4794.801us 5 5 100.00
edn_tl_intg_err 4.000s 429.745us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 38.565us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 12.000s 31.243us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.000s 4794.801us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.000s 4794.801us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 9.000s 4794.801us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 9.000s 4794.801us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 12.000s 31.243us 200 200 100.00
edn_sec_cm 9.000s 4794.801us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 12.000s 31.243us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.000s 429.745us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 30 76.67
edn_stress_all_with_rand_reset 104.000s 9701.135us 23 30 76.67

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
edn_stress_all_with_rand_reset 21557273942273197373414003193979439225493654320132438935416785855556215261224 189
UVM_INFO @ 979414633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 91535069650974985664667791052857206218542764828629053933565809974607875868764 194
UVM_INFO @ 611164958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 71064899672813274802656500983225039451986180246010907969709829171497251642190 370
UVM_INFO @ 2354393074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 78273071433559248707627466998246190938068347719124388799283421505610359921798 203
UVM_INFO @ 1841079620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 77145344051348443392131897740522541211641845302962518736043047586408004143959 249
UVM_INFO @ 1742203171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 96651969315449821970758168763894930362844958002735560249206080334834329607145 154
UVM_INFO @ 1010352585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 40599511333677078484402862018566099354642943225704606169805616215834508069418 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 54278366628260392472404240769163001868624845316346718217645589274811063514874 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 89576146472466717870234132556079928507642892977654359895606537212776792065585 105
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 98299214675857566701695075107912562795932826281005406611334190829422195765655 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 79458500741380831612841278590610532421529240402724237597694277888733197027700 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 59922344875199697645839991520444824622524966517361696738884121314745909982674 139
UVM_INFO @ 10047466756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 29904024483812769121106371492750365045983420977516752861440752580761912004500 103
UVM_INFO @ 57277495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---