Simulation Results: edn/edn1

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.04 %
  • code
  • 95.95 %
  • assert
  • 97.14 %
  • func
  • 92.02 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
99.01%
V2S
100.00%
V3
93.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.240s 45.021us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.190s 116.384us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.180s 54.406us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.610s 536.448us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.320s 49.414us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.440s 66.995us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.180s 54.406us 5 5 100.00
edn_csr_aliasing 1.320s 49.414us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.860s 863.575us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.860s 863.575us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.860s 863.575us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.210s 43.120us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.650s 131.528us 200 200 100.00
errs 100 100 100.00
edn_err 1.670s 30.835us 100 100 100.00
disable 94 100 94.00
edn_disable 1.180s 14.447us 50 50 100.00
edn_disable_auto_req_mode 10.970s 500.000us 44 50 88.00
stress_all 30 30 100.00
edn_stress_all 6.860s 414.665us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.170s 12.200us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.240s 19.148us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.280s 458.942us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.280s 458.942us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.190s 116.384us 1 1 100.00
edn_csr_rw 1.180s 54.406us 5 5 100.00
edn_csr_aliasing 1.320s 49.414us 1 1 100.00
edn_same_csr_outstanding 1.640s 72.793us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.190s 116.384us 1 1 100.00
edn_csr_rw 1.180s 54.406us 5 5 100.00
edn_csr_aliasing 1.320s 49.414us 1 1 100.00
edn_same_csr_outstanding 1.640s 72.793us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 5.860s 1491.475us 5 5 100.00
edn_tl_intg_err 3.030s 176.528us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.220s 29.660us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.650s 131.528us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.860s 1491.475us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.860s 1491.475us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.860s 1491.475us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.860s 1491.475us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.650s 131.528us 200 200 100.00
edn_sec_cm 5.860s 1491.475us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.650s 131.528us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.030s 176.528us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 28 30 93.33
edn_stress_all_with_rand_reset 84.130s 9223.482us 28 30 93.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 27529787203331241650852898334525375075910415459249022724586751623887535700037 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 19142816786445129465661541200624488129652742942709313984582634517238815292608 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 4065848791493116569651577971564229855181117136482822445189725136825138873695 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 99523915673841412504922346439601542867753632140403079529659072552303881921788 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 96457325503028293358050978357634581956616574189339255362794860024053375668247 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
edn_stress_all_with_rand_reset 13188169786653713366965168692202297734688592733243131214239005766598157169626 172
UVM_INFO @ 860100060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 71403338736703549331727526972455428790293684862736139058313872184644043522272 131
UVM_INFO @ 116618331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:425) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 11484669633559213644476326141344960892628665001345587963869301934416228034517 94
UVM_INFO @ 18138793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---