| V1 |
|
100.00% |
| V2 |
|
92.99% |
| V2S |
|
93.33% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 40 | 40 | 100.00 | |||
| gpio_smoke | 2.200s | 167.716us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 2.150s | 113.167us | 10 | 10 | 100.00 | |
| gpio_smoke_en_cdc_prim | 2.400s | 114.392us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.710s | 258.110us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 1.050s | 76.270us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| gpio_csr_rw | 1.100s | 82.681us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 10.770s | 5238.079us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 3.270s | 352.454us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.520s | 574.349us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| gpio_csr_rw | 1.100s | 82.681us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 3.270s | 352.454us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 20 | 20 | 100.00 | |||
| gpio_random_dout_din | 1.960s | 313.016us | 10 | 10 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.910s | 73.602us | 10 | 10 | 100.00 | |
| out_in_regs_read_write | 10 | 10 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.140s | 28.603us | 10 | 10 | 100.00 | |
| gpio_interrupt_programming | 10 | 10 | 100.00 | |||
| gpio_intr_rand_pgm | 2.040s | 808.819us | 10 | 10 | 100.00 | |
| random_interrupt_trigger | 10 | 10 | 100.00 | |||
| gpio_rand_intr_trigger | 5.100s | 179.735us | 10 | 10 | 100.00 | |
| interrupt_and_noise_filter | 10 | 10 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 3.460s | 64.462us | 10 | 10 | 100.00 | |
| noise_filter_stress | 10 | 10 | 100.00 | |||
| gpio_filter_stress | 27.020s | 3853.742us | 10 | 10 | 100.00 | |
| regs_long_reads_and_writes | 10 | 10 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 5.700s | 693.537us | 10 | 10 | 100.00 | |
| full_random | 10 | 10 | 100.00 | |||
| gpio_full_random | 1.510s | 148.192us | 10 | 10 | 100.00 | |
| stress_all | 1 | 10 | 10.00 | |||
| gpio_stress_all | 96.550s | 29314.061us | 1 | 10 | 10.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| gpio_alert_test | 0.880s | 37.234us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| gpio_intr_test | 0.970s | 14.585us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 4.670s | 886.234us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 4.670s | 886.234us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 10 | 12 | 83.33 | |||
| gpio_csr_rw | 1.100s | 82.681us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.720s | 63.657us | 3 | 5 | 60.00 | |
| gpio_csr_aliasing | 3.270s | 352.454us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.050s | 76.270us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 10 | 12 | 83.33 | |||
| gpio_csr_rw | 1.100s | 82.681us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.720s | 63.657us | 3 | 5 | 60.00 | |
| gpio_csr_aliasing | 3.270s | 352.454us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.050s | 76.270us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 28 | 30 | 93.33 | |||
| gpio_tl_intg_err | 3.390s | 685.792us | 23 | 25 | 92.00 | |
| gpio_sec_cm | 1.400s | 125.461us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 23 | 25 | 92.00 | |||
| gpio_tl_intg_err | 3.390s | 685.792us | 23 | 25 | 92.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 10 | 10 | 100.00 | |||
| gpio_rand_straps | 0.940s | 21.754us | 10 | 10 | 100.00 | |
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 23.980s | 5187.001us | 0 | 10 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 50 | 50 | 100.00 | |||
| gpio_inp_prd_cnt | 0.930s | 33.521us | 50 | 50 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:243) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 9 test runs | |||
| gpio_stress_all | 45051017021739474458845322078503966483070941955482835585307369278925154886566 | 606 |
UVM_INFO @ 582332196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 50291866558174063094601659690679032047114685886878864985253096553761217977939 | 83 |
UVM_INFO @ 967497221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 9614552904807806202117631393444119012720904913293035357596861948875698856402 | 83 |
UVM_INFO @ 294799178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 85744999622096681482986852695250582562452899586934057176186082599528319678441 | 244 |
UVM_INFO @ 240652758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 50654762989127685633980032730399869769743530409781944282661325392532139515947 | 696 |
UVM_INFO @ 7442124085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 58891892410210697342497415931449904171547624288415755055504056433951890398562 | 1379 |
UVM_INFO @ 20499327640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 85277009808191397094961255148627378001085930795739271277352545829757824929596 | 1539 |
UVM_INFO @ 29314060971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 11267195259502324232479726558457022670519303788849295078900623447702654607332 | 1817 |
UVM_INFO @ 151344271213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 73162140921045140316741765998345612471716553930969745664147438873645237596072 | 89 |
UVM_INFO @ 3017190700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 6 test runs | |||
| gpio_stress_all_with_rand_reset | 55003540651506395631407021644627358341115464609478979063623247619773846801382 | 84 |
UVM_INFO @ 12415478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 100276431101905362130009326043961004385663689934249636758796545757087185922592 | 84 |
UVM_INFO @ 33653536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 65454670135239708823427972826791736583999350505161635129434984699813289848107 | 571 |
UVM_INFO @ 5187000953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 1123765342169110597659289092568753190469594707312644996469513331790539580409 | 86 |
UVM_INFO @ 576031719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 3745728318684550315937307830310065568082187118637642836310806878479203966580 | 85 |
UVM_INFO @ 291496917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 16141052545691547334320968825816331396585677212083671946495073735796906083713 | 86 |
UVM_INFO @ 176862414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1230) [gpio_common_vseq] Check failed (vseq_done) | 4 test runs | |||
| gpio_stress_all_with_rand_reset | 48775396621608746539008213702424859352995788485109282708301040523310048871025 | 89 |
UVM_INFO @ 2869667947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 101934406552716212414587085539252888338976833059820017570598301936750650469603 | 88 |
UVM_INFO @ 318205737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 15473307828245926240526498152032534613059084738508312903489640566962209793828 | 86 |
UVM_INFO @ 10291528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 44386456748006530080972719104345001125537059830523560337486149693785440731595 | 86 |
UVM_INFO @ 15758556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 2 test runs | |||
| gpio_same_csr_outstanding | 32910599659547039206661821281869751042736015956611516360037693448630555194456 | 83 |
UVM_INFO @ 60759101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_same_csr_outstanding | 46520213069888514743606135990553462184810666388709340132515726847781459777263 | 83 |
UVM_INFO @ 20738153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_*.value_* reset value: * | 1 test run | |||
| gpio_tl_intg_err | 32963014220988243322986635403068476404108651265365613818925121920071057136599 | 110 |
UVM_INFO @ 19638457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: * | 1 test run | |||
| gpio_tl_intg_err | 102004398672947113334718675709163271360927813931296177333207786528778194828433 | 135 |
UVM_INFO @ 39019033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|