Simulation Results: hmac

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 96.11 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 23.000s 1438.067us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 21.197us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 22.001us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.000s 4173.014us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 158.055us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 20.568us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 22.001us 5 5 100.00
hmac_csr_aliasing 3.000s 158.055us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 90.000s 1826.844us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 121.000s 5908.253us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 364.000s 43282.352us 30 30 100.00
hmac_test_sha384_vectors 699.000s 337186.777us 75 75 100.00
hmac_test_sha512_vectors 702.000s 41701.714us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 5604.029us 50 50 100.00
hmac_test_hmac384_vectors 23.000s 1191.077us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 3626.543us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 45.000s 12389.690us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 440.000s 33378.463us 10 10 100.00
error 10 10 100.00
hmac_error 90.000s 2258.468us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 160.000s 12959.345us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 23.000s 1438.067us 10 10 100.00
hmac_long_msg 90.000s 1826.844us 10 10 100.00
hmac_back_pressure 121.000s 5908.253us 25 25 100.00
hmac_datapath_stress 440.000s 33378.463us 10 10 100.00
hmac_burst_wr 45.000s 12389.690us 50 50 100.00
hmac_stress_all 1243.000s 1573540.716us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 23.000s 1438.067us 10 10 100.00
hmac_long_msg 90.000s 1826.844us 10 10 100.00
hmac_back_pressure 121.000s 5908.253us 25 25 100.00
hmac_datapath_stress 440.000s 33378.463us 10 10 100.00
hmac_wipe_secret 160.000s 12959.345us 10 10 100.00
hmac_test_sha256_vectors 364.000s 43282.352us 30 30 100.00
hmac_test_sha384_vectors 699.000s 337186.777us 75 75 100.00
hmac_test_sha512_vectors 702.000s 41701.714us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 5604.029us 50 50 100.00
hmac_test_hmac384_vectors 23.000s 1191.077us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 3626.543us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 23.000s 1438.067us 10 10 100.00
hmac_long_msg 90.000s 1826.844us 10 10 100.00
hmac_back_pressure 121.000s 5908.253us 25 25 100.00
hmac_datapath_stress 440.000s 33378.463us 10 10 100.00
hmac_burst_wr 45.000s 12389.690us 50 50 100.00
hmac_error 90.000s 2258.468us 10 10 100.00
hmac_wipe_secret 160.000s 12959.345us 10 10 100.00
hmac_test_sha256_vectors 364.000s 43282.352us 30 30 100.00
hmac_test_sha384_vectors 699.000s 337186.777us 75 75 100.00
hmac_test_sha512_vectors 702.000s 41701.714us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 5604.029us 50 50 100.00
hmac_test_hmac384_vectors 23.000s 1191.077us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 3626.543us 75 75 100.00
hmac_stress_all 1243.000s 1573540.716us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1243.000s 1573540.716us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 28.894us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 13.000s 31.565us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 11.000s 186.751us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 11.000s 186.751us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.000s 21.197us 1 1 100.00
hmac_csr_rw 2.000s 22.001us 5 5 100.00
hmac_csr_aliasing 3.000s 158.055us 1 1 100.00
hmac_same_csr_outstanding 4.000s 479.427us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.000s 21.197us 1 1 100.00
hmac_csr_rw 2.000s 22.001us 5 5 100.00
hmac_csr_aliasing 3.000s 158.055us 1 1 100.00
hmac_same_csr_outstanding 4.000s 479.427us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 96.457us 5 5 100.00
hmac_tl_intg_err 11.000s 385.239us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 11.000s 385.239us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 23.000s 1438.067us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.000s 135.583us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 746.000s 59717.760us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 53.553us 1 1 100.00