Simulation Results: lc_ctrl/volatile_unlock_disabled

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.24 %
  • code
  • 93.20 %
  • assert
  • 96.83 %
  • func
  • 89.68 %
  • block
  • 96.70 %
  • line
  • 97.39 %
  • branch
  • 91.61 %
  • toggle
  • 88.57 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.13%
V2S
98.67%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.000s 381.568us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 28.000s 44.903us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 28.000s 13.800us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 28.000s 259.427us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 28.000s 52.998us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 28.000s 104.156us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 28.000s 13.800us 5 5 100.00
lc_ctrl_csr_aliasing 28.000s 52.998us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 3.000s 231.530us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 10.000s 1662.522us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 28.000s 38.235us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 134.673us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 7.000s 334.195us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 31.000s 326.359us 20 20 100.00
security_escalation 134 140 95.71
lc_ctrl_state_failure 7.000s 334.195us 20 20 100.00
lc_ctrl_prog_failure 4.000s 134.673us 20 20 100.00
lc_ctrl_errors 31.000s 326.359us 20 20 100.00
lc_ctrl_security_escalation 7.000s 2021.895us 20 20 100.00
lc_ctrl_jtag_state_failure 22.000s 26781.305us 17 20 85.00
lc_ctrl_jtag_prog_failure 10.000s 1181.424us 18 20 90.00
lc_ctrl_jtag_errors 26.000s 3530.585us 19 20 95.00
jtag_access 205 210 97.62
lc_ctrl_jtag_smoke 9.000s 774.963us 20 20 100.00
lc_ctrl_jtag_state_post_trans 13.000s 2855.061us 18 20 90.00
lc_ctrl_jtag_prog_failure 10.000s 1181.424us 18 20 90.00
lc_ctrl_jtag_errors 26.000s 3530.585us 19 20 95.00
lc_ctrl_jtag_access 27.000s 6908.320us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 13.000s 1161.284us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 15.000s 302.857us 10 10 100.00
lc_ctrl_jtag_csr_rw 8.000s 295.276us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 31.000s 7165.469us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 27.000s 7100.366us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 165.081us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 12.000s 1025.169us 10 10 100.00
lc_ctrl_jtag_alert_test 24.000s 1415.028us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 7.000s 456.668us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 25.956us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 196.000s 85075.973us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 28.000s 127.066us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 3.000s 46.567us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 3.000s 46.567us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 28.000s 44.903us 1 1 100.00
lc_ctrl_csr_rw 28.000s 13.800us 5 5 100.00
lc_ctrl_csr_aliasing 28.000s 52.998us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 42.609us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 28.000s 44.903us 1 1 100.00
lc_ctrl_csr_rw 28.000s 13.800us 5 5 100.00
lc_ctrl_csr_aliasing 28.000s 52.998us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 42.609us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 4.000s 289.413us 5 5 100.00
lc_ctrl_tl_intg_err 3.000s 250.007us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.000s 250.007us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 10.000s 1662.522us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 334.195us 20 20 100.00
lc_ctrl_sec_cm 4.000s 289.413us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 334.195us 20 20 100.00
lc_ctrl_sec_cm 4.000s 289.413us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 334.195us 20 20 100.00
lc_ctrl_sec_cm 4.000s 289.413us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 334.195us 20 20 100.00
lc_ctrl_sec_cm 4.000s 289.413us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 334.195us 20 20 100.00
lc_ctrl_sec_cm 4.000s 289.413us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 334.195us 20 20 100.00
lc_ctrl_sec_cm 4.000s 289.413us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 334.195us 20 20 100.00
lc_ctrl_sec_cm 4.000s 289.413us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 7.000s 334.195us 20 20 100.00
lc_ctrl_sec_cm 4.000s 289.413us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 7.000s 2021.895us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 38 40 95.00
lc_ctrl_state_post_trans 3.000s 231.530us 20 20 100.00
lc_ctrl_jtag_state_post_trans 13.000s 2855.061us 18 20 90.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.000s 2254.126us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.000s 2254.126us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 7.000s 539.169us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.000s 1321.583us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.000s 1321.583us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 36.000s 8528.159us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 5 test runs
lc_ctrl_jtag_state_failure 37007599716356303781927342763540932822597763106906454740524853392880048206772 175
UVM_INFO @ 63562050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 81609884100360918699507788157591461314932439290616552831820470316468329252249 175
UVM_INFO @ 332647368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 113695877577785589771587559255105375455064307713994006863907557331907635632258 175
UVM_INFO @ 74472078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 2921627247801872534938854935550697908412860187521380109981965677946028200519 175
UVM_INFO @ 314234918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 114068549244799997930537293774883560870081759946180745693719931011217980268250 175
UVM_INFO @ 462414056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 13349220920464575985592603651517396392207409817041601893330719839514986034223 1408
UVM_INFO @ 13636427128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80599288018337645971781044621213621989162357019162620575138797984058373435992 4544
UVM_INFO @ 2784800951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 40283295438339745447359496906571868648934579286654949852741102556849734196503 2723
UVM_INFO @ 8528159178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 66076363913710057589696085565622450682042129639654927159458073829979250133939 4138
UVM_INFO @ 4247415621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75848897478210275819692906348999971261170386724546776035798096345945951658660 4455
UVM_INFO @ 2679599955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 3 test runs
lc_ctrl_jtag_prog_failure 28553791349946980425036601131828684711247830269024415586515853545680675691182 177
UVM_INFO @ 277465061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 35342396023369869466921369394387724304424355882092463860540696880436895373792 175
UVM_INFO @ 324169521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 26385196574527124418253630586074521393616343908483400636873265648155543205572 176
UVM_INFO @ 90764824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---