Simulation Results: lc_ctrl/volatile_unlock_enabled

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.25 %
  • code
  • 94.18 %
  • assert
  • 96.54 %
  • func
  • 89.03 %
  • block
  • 97.16 %
  • line
  • 97.72 %
  • branch
  • 92.79 %
  • toggle
  • 88.60 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.06%
V2S
99.33%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.000s 276.510us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 81.728us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 25.763us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 227.221us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 105.111us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 488.182us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 25.763us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 105.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 3.000s 292.111us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 8.000s 551.183us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 44.034us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.000s 536.425us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 7.000s 1829.935us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 7.000s 348.271us 20 20 100.00
security_escalation 137 140 97.86
lc_ctrl_state_failure 7.000s 1829.935us 20 20 100.00
lc_ctrl_prog_failure 3.000s 536.425us 20 20 100.00
lc_ctrl_errors 7.000s 348.271us 20 20 100.00
lc_ctrl_security_escalation 7.000s 888.796us 20 20 100.00
lc_ctrl_jtag_state_failure 30.000s 3613.042us 18 20 90.00
lc_ctrl_jtag_prog_failure 8.000s 841.695us 19 20 95.00
lc_ctrl_jtag_errors 32.000s 43255.792us 20 20 100.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 6.000s 643.700us 20 20 100.00
lc_ctrl_jtag_state_post_trans 10.000s 3518.589us 19 20 95.00
lc_ctrl_jtag_prog_failure 8.000s 841.695us 19 20 95.00
lc_ctrl_jtag_errors 32.000s 43255.792us 20 20 100.00
lc_ctrl_jtag_access 10.000s 5542.609us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 4210.976us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 265.872us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 104.363us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 12.000s 3157.211us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 9.000s 5496.093us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 52.282us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 3196.620us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 85.855us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 20.000s 2991.511us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 94.723us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 116.000s 41224.939us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 2.000s 76.688us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 42.634us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 42.634us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.000s 81.728us 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.763us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 105.111us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 251.376us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.000s 81.728us 1 1 100.00
lc_ctrl_csr_rw 2.000s 25.763us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 105.111us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 251.376us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 4.000s 991.652us 5 5 100.00
lc_ctrl_tl_intg_err 3.000s 1222.025us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.000s 1222.025us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 8.000s 551.183us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 1829.935us 20 20 100.00
lc_ctrl_sec_cm 4.000s 991.652us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 1829.935us 20 20 100.00
lc_ctrl_sec_cm 4.000s 991.652us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 1829.935us 20 20 100.00
lc_ctrl_sec_cm 4.000s 991.652us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 1829.935us 20 20 100.00
lc_ctrl_sec_cm 4.000s 991.652us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 1829.935us 20 20 100.00
lc_ctrl_sec_cm 4.000s 991.652us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 1829.935us 20 20 100.00
lc_ctrl_sec_cm 4.000s 991.652us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 1829.935us 20 20 100.00
lc_ctrl_sec_cm 4.000s 991.652us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 7.000s 1829.935us 20 20 100.00
lc_ctrl_sec_cm 4.000s 991.652us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 7.000s 888.796us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 39 40 97.50
lc_ctrl_state_post_trans 3.000s 292.111us 20 20 100.00
lc_ctrl_jtag_state_post_trans 10.000s 3518.589us 19 20 95.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.000s 1275.711us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.000s 1275.711us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 7.000s 2109.062us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 6.000s 915.907us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 6.000s 915.907us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 51.000s 11157.260us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 66471161196781759300578429310900246022419218459594373861255845364523233333125 3800
UVM_INFO @ 5441938494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98385983894800040738011074161647078015934150845675184752371522024113505197395 1339
UVM_INFO @ 720112834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101570065557854133426783713811499805974537197088024466626683656695498225697170 7582
UVM_INFO @ 61127858113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48980875768470625887911705226905942478275774451303635521276370400775211895156 160
UVM_INFO @ 551294099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 3 test runs
lc_ctrl_jtag_state_post_trans 73054523160972526804220069654061393839415173242534326833154500438998353629890 176
UVM_INFO @ 874767620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 81027848696220888971582125521436395415615001243237351969809308541147659285717 179
UVM_INFO @ 58551718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 11143745274166694705753562876789427985051823318150311930693037102782718176972 175
UVM_INFO @ 17888285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:933) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 97851350012837127076225903568516307038788602432143884602253159180558234048726 3334
UVM_INFO @ 82494762556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 59871442209825843074083602337718092601343883018510311092737717494121659230059 175
UVM_INFO @ 499218171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---