Simulation Results: otbn

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.75 %
  • code
  • 87.11 %
  • assert
  • 97.14 %
  • func
  • 100.00 %
  • block
  • 99.37 %
  • line
  • 99.55 %
  • branch
  • 95.39 %
  • toggle
  • 85.89 %
  • FSM
  • 67.61 %
Validation stages
V1
99.15%
V2
99.39%
V2S
97.87%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 12.000s 58.739us 1 1 100.00
otbn_smoke_vectorized 9.000s 59.275us 1 1 100.00
single_binary 99 100 99.00
otbn_single 303.000s 1074.936us 99 100 99.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 9.000s 45.706us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 9.000s 26.767us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 12.000s 80.240us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 10.000s 12.937us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 13.000s 309.649us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 9.000s 26.767us 5 5 100.00
otbn_csr_aliasing 10.000s 12.937us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 78.000s 5697.048us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 29.000s 2269.897us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 47.000s 318.506us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 75.000s 176.482us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 222.000s 582.154us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 133.000s 369.219us 10 10 100.00
lc_escalation 59 60 98.33
otbn_escalate 25.000s 146.309us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 10.000s 17.544us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 26.000s 314.005us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 11.000s 18.354us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 9.000s 28.005us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 9.000s 135.074us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 9.000s 135.074us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 9.000s 45.706us 1 1 100.00
otbn_csr_rw 9.000s 26.767us 5 5 100.00
otbn_csr_aliasing 10.000s 12.937us 1 1 100.00
otbn_same_csr_outstanding 7.000s 268.227us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 9.000s 45.706us 1 1 100.00
otbn_csr_rw 9.000s 26.767us 5 5 100.00
otbn_csr_aliasing 10.000s 12.937us 1 1 100.00
otbn_same_csr_outstanding 7.000s 268.227us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 14.000s 36.228us 10 10 100.00
otbn_dmem_err 47.000s 157.981us 15 15 100.00
internal_integrity 16 17 94.12
otbn_alu_bignum_mod_err 34.000s 98.112us 5 5 100.00
otbn_controller_ispr_rdata_err 13.000s 282.038us 5 5 100.00
otbn_mac_bignum_acc_err 14.000s 255.369us 5 5 100.00
otbn_urnd_err 6.000s 100.795us 1 2 50.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 9.000s 19.770us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 10.000s 23.227us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 9.000s 44.526us 9 10 90.00
tl_intg_err 29 30 96.67
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
otbn_tl_intg_err 103.000s 570.014us 25 25 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 105.000s 504.189us 4 5 80.00
prim_fsm_check 4 5 80.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
prim_count_check 4 5 80.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 58.739us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 47.000s 157.981us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 14.000s 36.228us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 103.000s 570.014us 25 25 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 25.000s 146.309us 59 60 98.33
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 14.000s 36.228us 10 10 100.00
otbn_dmem_err 47.000s 157.981us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 17.544us 5 5 100.00
otbn_illegal_mem_acc 9.000s 19.770us 5 5 100.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_controller_fsm_sparse 4 5 80.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 303.000s 1074.936us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 14.000s 36.228us 10 10 100.00
otbn_dmem_err 47.000s 157.981us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 17.544us 5 5 100.00
otbn_illegal_mem_acc 9.000s 19.770us 5 5 100.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_scramble_ctrl_fsm_sparse 4 5 80.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 25.000s 146.309us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 14.000s 36.228us 10 10 100.00
otbn_dmem_err 47.000s 157.981us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 17.544us 5 5 100.00
otbn_illegal_mem_acc 9.000s 19.770us 5 5 100.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_start_stop_ctrl_fsm_sparse 4 5 80.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 303.000s 1074.936us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 12.000s 33.193us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 44.842us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 42.000s 805.581us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 42.000s 805.581us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 13.000s 38.976us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 4 5 80.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_stack_wr_ptr_ctr_redun 4 5 80.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 14.000s 71.156us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 4 5 80.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_loop_stack_ctr_redun 4 5 80.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 28.000s 77.171us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 28.000s 77.171us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 38.000s 119.971us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 303.000s 1074.936us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 303.000s 1074.936us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 303.000s 1074.936us 99 100 99.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 222.000s 582.154us 10 10 100.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 303.000s 1074.936us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 303.000s 1074.936us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 29.000s 91.083us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 303.000s 1074.936us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 4 5 80.00
otbn_sec_cm 454.000s 2122.506us 4 5 80.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 392.000s 1556.665us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
otbn_stress_all_with_rand_reset 25658776997174363433229154559718920820126133408028725611089642755289875458664 160
UVM_INFO @ 143879491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 111490351005771275614262783672575978362836071677908809437811303255680440724396 337
UVM_INFO @ 5143494984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 84497499028812757242014108399974040695739155268933383902325132292460840096214 352
UVM_INFO @ 1556665406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 106388130275736439013264400605291760533369511622028916324341221735326211956290 203
UVM_INFO @ 265103865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 35133118720657709039372462691550669536377792183299210021443199931873925030692 168
UVM_INFO @ 1105797453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 2 test runs
otbn_urnd_err 16238671298005330937986524466673762466844335177873348893727895593158465359354 116
UVM_ERROR @ 100795412 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 100795412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 6996967101744218192499201307243733065650185993564446556885854546061349603592 104
UVM_ERROR @ 5992384 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 5992384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 2 test runs
otbn_single 35304927309266351884538508016018158734269190465316323205612144092122225111507 110
UVM_INFO @ 54644839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 112832221873803052874455453961061824835184424890811953425845146400485988255414 86
UVM_INFO @ 3992605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_rnd.sv,233): Assertion UrndNoReseedOnReset_A has failed 1 test run
otbn_sec_cm 78296906817355048438671432914180772577610116005389282577656251217871468317358 236
UVM_ERROR @ 215707164 ps: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 215707164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 99861587949190233430685733331917069020829853012109825956604866232784490667304 394
UVM_INFO @ 1298320254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_rf_bignum_intg_err 105863802401952346334504861817779553363811539839050223714912567789297902282786 111
UVM_INFO @ 38783947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_escalate 112708893876016619850137356082188320280460548872402412914020502713277485322245 115
UVM_ERROR @ 18726419 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 18726419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---