Simulation Results: rom_ctrl/32kb

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.48 %
  • code
  • 86.62 %
  • assert
  • 97.53 %
  • func
  • 99.29 %
  • block
  • 79.88 %
  • line
  • 79.78 %
  • branch
  • 82.01 %
  • toggle
  • 84.69 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
66.10%
V3
95.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 3.000s 224.615us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 2.000s 56.832us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 2.000s 67.854us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 84.364us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 88.852us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 69.808us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 2.000s 67.854us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 88.852us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 75.347us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 57.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 3.000s 173.305us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 10.000s 812.631us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 2.000s 56.123us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 3.000s 49.665us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 7.000s 208.184us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 7.000s 208.184us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 2.000s 56.832us 1 1 100.00
rom_ctrl_csr_rw 2.000s 67.854us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 88.852us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 507.172us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 2.000s 56.832us 1 1 100.00
rom_ctrl_csr_rw 2.000s 67.854us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 88.852us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 507.172us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1859.000s 1000000.000us 0 20 0.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 1062.938us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 98.000s 1164.898us 5 5 100.00
rom_ctrl_tl_intg_err 27.000s 225.377us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 98.000s 1164.898us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 98.000s 1164.898us 5 5 100.00
sec_cm_checker_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1859.000s 1000000.000us 0 20 0.00
sec_cm_checker_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1859.000s 1000000.000us 0 20 0.00
sec_cm_checker_fsm_local_esc 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1859.000s 1000000.000us 0 20 0.00
sec_cm_compare_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1859.000s 1000000.000us 0 20 0.00
sec_cm_compare_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1859.000s 1000000.000us 0 20 0.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 98.000s 1164.898us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 98.000s 1164.898us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 3.000s 224.615us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 3.000s 224.615us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 3.000s 224.615us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 27.000s 225.377us 25 25 100.00
sec_cm_bus_local_esc 2 22 9.09
rom_ctrl_corrupt_sig_fatal_chk 1859.000s 1000000.000us 0 20 0.00
rom_ctrl_kmac_err_chk 2.000s 56.123us 2 2 100.00
sec_cm_mux_mubi 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1859.000s 1000000.000us 0 20 0.00
sec_cm_mux_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1859.000s 1000000.000us 0 20 0.00
sec_cm_ctrl_redun 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1859.000s 1000000.000us 0 20 0.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 1062.938us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 98.000s 1164.898us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 19 20 95.00
rom_ctrl_stress_all_with_rand_reset 71.000s 4491.255us 19 20 95.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 10 test runs
rom_ctrl_corrupt_sig_fatal_chk 59547945533165201529667414528303998410580198213605083845002176462782435333475 90
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 41647428225309490453785184099837734309091209832985865701093209067440037690474 88
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 12931858164567842008386792816627273098969677027115048828932141956954654719994 90
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 47056354490255583386369808629787125139950604542931310752633049259188457740928 94
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 75030939417136269128460912780536548416559557722980861273345816217657814688258 87
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 50800698732248261312468495534895772050233281979075710080749306094213420593466 88
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 76483736629147369391826824210387180865424971098701965323843110731831875550994 96
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 4209732148607026281731004566711949591213206901919970924481148480093170904214 88
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 48660199187290140017163737555519897987293964819688013442676722468885943404583 95
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 50757352223722638099055433036829225057075239680676939253544947388268364007559 87
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:154) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data_o_i.done != MuBi4True) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 14915503530609512512544189227574879150453161841241354761512407990647348582078 88
UVM_INFO @ 11874450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 36933274078965935196727627580885028396368589106682760681195057371384940001046 87
UVM_INFO @ 48633121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 41818658211684831974230275660993180232182839420026668297183211394515432099665 87
UVM_INFO @ 20099114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:301) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.compare_vif.is_waiting()) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 79296685507170579823722541961280988270388833983943174856486336612719126196305 87
UVM_INFO @ 9287259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 87949277936094577611109684422154367879149096428582421863948816305680475961116 87
UVM_INFO @ 8294544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 48842565542494043681665843778330500939979195461119876860299311122690535073379 87
UVM_INFO @ 6304646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 30983164882318218859424796955922676021394189731984512813530301517685551780831 88
UVM_INFO @ 170247476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 46088345626663375077709312133638888889239748680377572495274012897176496230336 88
UVM_INFO @ 173305476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:284) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 8594557976334422188849231399244754655026226862008741156302707062241595041791 88
UVM_INFO @ 9139444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 9701050284973976624927333517473255911098503094050736448585325648848245060268 87
UVM_INFO @ 7463943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles. 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 16898225958832479457246703703614577000665009151291943058495143009240993073483 89
UVM_INFO @ 109488038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 7236436312723774920453112208177254438999020289213705319763679030018113114998 90
UVM_INFO @ 112677560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 1 test run
rom_ctrl_stress_all_with_rand_reset 113123804359165166581990553192015428707025588485808270755822038531722681648425 93
UVM_INFO @ 1170576976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---