Simulation Results

Simulation Results: rom_ctrl/64kb

14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.42 %

code
80.31 %

assert
97.67 %

func
99.29 %

block
79.47 %

line
79.69 %

branch
80.61 %

toggle
84.74 %

FSM
76.19 %

Validation stages

V1		100.00%
V2		95.77%
V2S		66.10%
V3		80.00%

17/17 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rom_ctrl_smoke	4.000s	1399.317us	2	2	100.00
csr_hw_reset				1	1	100.00
	rom_ctrl_csr_hw_reset	4.000s	86.452us	1	1	100.00
csr_rw				5	5	100.00
	rom_ctrl_csr_rw	4.000s	57.287us	5	5	100.00
csr_bit_bash				1	1	100.00
	rom_ctrl_csr_bit_bash	3.000s	111.025us	1	1	100.00
csr_aliasing				1	1	100.00
	rom_ctrl_csr_aliasing	3.000s	63.046us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rom_ctrl_csr_mem_rw_with_rand_reset	4.000s	92.424us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rom_ctrl_csr_rw	4.000s	57.287us	5	5	100.00
	rom_ctrl_csr_aliasing	3.000s	63.046us	1	1	100.00
mem_walk				1	1	100.00
	rom_ctrl_mem_walk	3.000s	58.739us	1	1	100.00
mem_partial_access				1	1	100.00
	rom_ctrl_mem_partial_access	2.000s	71.195us	1	1	100.00

68/71 passed

95.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
max_throughput_chk				0	2	0.00
	rom_ctrl_max_throughput_chk	4.000s	676.543us	0	2	0.00
stress_all				19	20	95.00
	rom_ctrl_stress_all	247.000s	1000000.000us	19	20	95.00
kmac_err_chk				2	2	100.00
	rom_ctrl_kmac_err_chk	10.000s	719.443us	2	2	100.00
alert_test				10	10	100.00
	rom_ctrl_alert_test	4.000s	73.893us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rom_ctrl_tl_errors	8.000s	1471.673us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rom_ctrl_tl_errors	8.000s	1471.673us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rom_ctrl_csr_hw_reset	4.000s	86.452us	1	1	100.00
	rom_ctrl_csr_rw	4.000s	57.287us	5	5	100.00
	rom_ctrl_csr_aliasing	3.000s	63.046us	1	1	100.00
	rom_ctrl_same_csr_outstanding	4.000s	137.560us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rom_ctrl_csr_hw_reset	4.000s	86.452us	1	1	100.00
	rom_ctrl_csr_rw	4.000s	57.287us	5	5	100.00
	rom_ctrl_csr_aliasing	3.000s	63.046us	1	1	100.00
	rom_ctrl_same_csr_outstanding	4.000s	137.560us	5	5	100.00

V2S

39/59 passed

66.10 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
corrupt_sig_fatal_chk				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2146.000s	1000000.000us	0	20	0.00
passthru_mem_tl_intg_err				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	17.000s	2088.690us	5	5	100.00
tl_intg_err				30	30	100.00
	rom_ctrl_sec_cm	225.000s	881.748us	5	5	100.00
	rom_ctrl_tl_intg_err	61.000s	784.830us	25	25	100.00
prim_fsm_check				5	5	100.00
	rom_ctrl_sec_cm	225.000s	881.748us	5	5	100.00
prim_count_check				5	5	100.00
	rom_ctrl_sec_cm	225.000s	881.748us	5	5	100.00
sec_cm_checker_ctr_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2146.000s	1000000.000us	0	20	0.00
sec_cm_checker_ctrl_flow_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2146.000s	1000000.000us	0	20	0.00
sec_cm_checker_fsm_local_esc				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2146.000s	1000000.000us	0	20	0.00
sec_cm_compare_ctrl_flow_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2146.000s	1000000.000us	0	20	0.00
sec_cm_compare_ctr_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2146.000s	1000000.000us	0	20	0.00
sec_cm_compare_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	225.000s	881.748us	5	5	100.00
sec_cm_fsm_sparse				5	5	100.00
	rom_ctrl_sec_cm	225.000s	881.748us	5	5	100.00
sec_cm_mem_scramble				2	2	100.00
	rom_ctrl_smoke	4.000s	1399.317us	2	2	100.00
sec_cm_mem_digest				2	2	100.00
	rom_ctrl_smoke	4.000s	1399.317us	2	2	100.00
sec_cm_intersig_mubi				2	2	100.00
	rom_ctrl_smoke	4.000s	1399.317us	2	2	100.00
sec_cm_bus_integrity				25	25	100.00
	rom_ctrl_tl_intg_err	61.000s	784.830us	25	25	100.00
sec_cm_bus_local_esc				2	22	9.09
	rom_ctrl_corrupt_sig_fatal_chk	2146.000s	1000000.000us	0	20	0.00
	rom_ctrl_kmac_err_chk	10.000s	719.443us	2	2	100.00
sec_cm_mux_mubi				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2146.000s	1000000.000us	0	20	0.00
sec_cm_mux_consistency				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2146.000s	1000000.000us	0	20	0.00
sec_cm_ctrl_redun				0	20	0.00
	rom_ctrl_corrupt_sig_fatal_chk	2146.000s	1000000.000us	0	20	0.00
sec_cm_ctrl_mem_integrity				5	5	100.00
	rom_ctrl_passthru_mem_tl_intg_err	17.000s	2088.690us	5	5	100.00
sec_cm_tlul_fifo_ctr_redun				5	5	100.00
	rom_ctrl_sec_cm	225.000s	881.748us	5	5	100.00

16/20 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				16	20	80.00
	rom_ctrl_stress_all_with_rand_reset	62.000s	76482.913us	16	20	80.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				9 test runs
	rom_ctrl_corrupt_sig_fatal_chk	108282107780436073944445353185723553469524231901886567256795926797760129249897	87	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	588643379325687069479100441718631013818876865524135546388236928650284200935	90	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	22521035521645758941881637471458439752721054326089325707503398134825845584424	87	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	107116895557869271156985058643674717977241182675573231403644868963279606959321	91	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	104077056577388296824252215946274185168349446117084153765880542057865335153691	92	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all	22588087212866737717508905870886936831052345988384267885706407197389607686745	88	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	95593097061367906097633133673498640912514814800995319259940626277457148014270	87	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	4350042728285183440933695376999538889056130087367027217978024458345350322284	99	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	96601997505189830164531243860812469115606552272488805281087056260681800719030	87	UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles.				5 test runs
	rom_ctrl_corrupt_sig_fatal_chk	97418511315143211502973710039764030785647256620534628112101878620775607804554	89	UVM_INFO @ 18784763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	74538012840371234443324182602310740067248553766361899260761180085147160614320	87	UVM_INFO @ 13523724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	67400231759467056622314537160412170092910585441862952333916063496546422550814	87	UVM_INFO @ 54195635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	77362232787261228735204724028278373560403031294995919019388183339772074785416	89	UVM_INFO @ 1523054199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	14031430514742414958803353480630205290148176897016185359771461926589843576959	87	UVM_INFO @ 68244593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:*				4 test runs
	rom_ctrl_stress_all_with_rand_reset	73306344928092223963836037711009135371279072696058162081956341982879030753811	95	UVM_INFO @ 606964318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	2010042608619610468437070986530475530309889479341717629674826530190624801583	89	UVM_INFO @ 101462544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	86149247356146108165238812501825563190068199768145672042353143916470681003849	89	UVM_INFO @ 144416098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_stress_all_with_rand_reset	87827896872379027626535427117890826172111661023394591695873225264163428310953	92	UVM_INFO @ 520706257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:154) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data_o_i.done != MuBi4True)				3 test runs
	rom_ctrl_corrupt_sig_fatal_chk	29752227607415131732954132276860194361999785151846736981459557183109455664438	89	UVM_INFO @ 34150267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	110856995209915837702296109895877623197809074147868082274943035016901801488675	88	UVM_INFO @ 77422627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	101932427940963144762628900471481441447199887910892166257334845207729926155220	91	UVM_INFO @ 74737810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:284) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow)				3 test runs
	rom_ctrl_corrupt_sig_fatal_chk	22864182230525624978393676775505140652467863119345429525959880046299618213409	88	UVM_INFO @ 32214213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	64926922186589131519414882965257908413791294670122587187715918756999868964028	91	UVM_INFO @ 29790572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_corrupt_sig_fatal_chk	76785146730705154397812887208881630340439332636264702452489915276119921438339	87	UVM_INFO @ 1731899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [] vs [*])				2 test runs
	rom_ctrl_max_throughput_chk	111190306187342555020110054494506191600563600713651219269694445522105042794503	88	UVM_INFO @ 4611553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_ctrl_max_throughput_chk	70528406634971520783953224263437896410761780876529308082306802555825456284045	88	UVM_INFO @ 676542980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:301) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.compare_vif.is_waiting())				1 test run
	rom_ctrl_corrupt_sig_fatal_chk	56887338909864031481070012880770866004751630201476247109760424065538986393656	87	UVM_INFO @ 6648864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---