Simulation Results: rstmgr

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.67 %
  • code
  • 99.59 %
  • assert
  • 98.53 %
  • func
  • 97.89 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 1.780s 58.148us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.590s 93.242us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.350s 36.790us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.730s 209.279us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.640s 43.563us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.410s 98.023us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.350s 36.790us 5 5 100.00
rstmgr_csr_aliasing 1.640s 43.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 2.800s 212.781us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 1.730s 48.969us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.490s 55.379us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 7.550s 719.186us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 7.550s 719.186us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 7.550s 719.186us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 7.550s 719.186us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 30.230s 2472.810us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.360s 42.179us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 3.290s 89.761us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 3.290s 89.761us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.590s 93.242us 1 1 100.00
rstmgr_csr_rw 1.350s 36.790us 5 5 100.00
rstmgr_csr_aliasing 1.640s 43.563us 1 1 100.00
rstmgr_same_csr_outstanding 1.650s 45.323us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.590s 93.242us 1 1 100.00
rstmgr_csr_rw 1.350s 36.790us 5 5 100.00
rstmgr_csr_aliasing 1.640s 43.563us 1 1 100.00
rstmgr_same_csr_outstanding 1.650s 45.323us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rstmgr_sec_cm 71.250s 9813.878us 5 5 100.00
rstmgr_tl_intg_err 8.230s 692.706us 25 25 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 71.250s 9813.878us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 71.250s 9813.878us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
rstmgr_tl_intg_err 8.230s 692.706us 25 25 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.680s 72.600us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 24 25 96.00
rstmgr_leaf_rst_cnsty 5.940s 422.378us 24 25 96.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 3.610s 297.606us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 71.250s 9813.878us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.350s 36.790us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.350s 36.790us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* 1 test run
rstmgr_leaf_rst_cnsty 90018718280262963252092771946694112745393103313134008382861070725376596616562 123
UVM_INFO @ 224059647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---