Simulation Results

Simulation Results: rv_dm/use_dmi_interface

14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.45 %

code
83.11 %

assert
96.90 %

func
97.34 %

block
93.57 %

line
94.12 %

branch
82.57 %

toggle
75.39 %

FSM
80.36 %

Validation stages

V1		96.92%
V2		44.44%
V2S		92.00%
V3		5.00%
unmapped		0.00%

126/130 passed

96.92 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	37.000s	2565.473us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	50.000s	480.582us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	52.000s	615.209us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	96.000s	30882.093us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	41.000s	1453.880us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	49.000s	9280.752us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	63.000s	13071.418us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	145.000s	53251.579us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	171.000s	105180.481us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	37.000s	1010.205us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	46.000s	608.100us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	48.000s	420.898us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	46.000s	125.433us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	44.000s	136.162us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	39.000s	510.448us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	50.000s	309.062us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	49.000s	1502.148us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	37.000s	1010.205us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	47.000s	321.059us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	44.000s	1321.947us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	48.000s	420.898us	2	2	100.00
rom_read_access				0	2	0.00
	rv_dm_rom_read_access	46.000s	32.861us	0	2	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	35.000s	475.428us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	52.000s	147.346us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	71.000s	17490.909us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	70.000s	6988.960us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	47.000s	40.115us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	70.000s	6988.960us	1	1	100.00
	rv_dm_csr_rw	52.000s	147.346us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	37.000s	48.075us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	32.000s	51.472us	1	1	100.00

80/180 passed

44.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	37.000s	2565.473us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	36.000s	136.022us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	44.000s	300.265us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	54.000s	296.413us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	43.000s	654.089us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	56.000s	7566.523us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	49.000s	181.725us	0	20	0.00
bad_sba				2	20	10.00
	rv_dm_bad_sba_tl_access	55.000s	3039.165us	2	20	10.00
sba_autoincrement				5	20	25.00
	rv_dm_autoincr_sba_tl_access	89.000s	76371.841us	5	20	25.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	47.000s	203.117us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	46.000s	2169.706us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	45.000s	236.644us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	46.000s	74.388us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	52.000s	16113.414us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	95.000s	4500.085us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	32.000s	162.045us	1	1	100.00
stress_all				0	20	0.00
	rv_dm_stress_all	10802.139s	0.000us	0	20	0.00
alert_test				10	10	100.00
	rv_dm_alert_test	45.000s	86.403us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	51.000s	256.408us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	51.000s	256.408us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	70.000s	6988.960us	1	1	100.00
	rv_dm_csr_hw_reset	35.000s	475.428us	1	1	100.00
	rv_dm_csr_rw	52.000s	147.346us	5	5	100.00
	rv_dm_same_csr_outstanding	51.000s	162.015us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	70.000s	6988.960us	1	1	100.00
	rv_dm_csr_hw_reset	35.000s	475.428us	1	1	100.00
	rv_dm_csr_rw	52.000s	147.346us	5	5	100.00
	rv_dm_same_csr_outstanding	51.000s	162.015us	5	5	100.00

V2S

46/50 passed

92.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	56.000s	2841.099us	5	5	100.00
	rv_dm_tl_intg_err	56.000s	1893.480us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	56.000s	1893.480us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	46.000s	2169.706us	2	2	100.00
	rv_dm_debug_disabled	37.000s	70.248us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	46.000s	2169.706us	2	2	100.00
	rv_dm_debug_disabled	37.000s	70.248us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	37.000s	2565.473us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				6	10	60.00
	rv_dm_buffered_enable	48.000s	165.245us	6	10	60.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	45.000s	78.700us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	45.000s	78.700us	4	4	100.00
sec_cm_exec_ctrl_mubi				6	10	60.00
	rv_dm_buffered_enable	48.000s	165.245us	6	10	60.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	20	5.00
	rv_dm_stress_all_with_rand_reset	74.000s	1433.462us	1	20	5.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	278.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared:				37 test runs
	rv_dm_sba_tl_access	114197097689017059353805285836300018314871422650120443896087498144573509785110	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23808
	rv_dm_sba_tl_access	21482840781234146778927421920665686887959326736017402161119896059290488305252	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23792
	rv_dm_bad_sba_tl_access	6718072802391858658197400092642657377937664771656751061551653047158392260797	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23954
	rv_dm_autoincr_sba_tl_access	3752182296926173038226268930828540797244751805028627527306125115036746237291	123	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23935
	rv_dm_sba_tl_access	49020527332293640145797193930806761192435458950902946647374439729278557038402	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23866
	rv_dm_autoincr_sba_tl_access	34287086852627188704146209067867067509897328894900311601333879863565025232559	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23964
	rv_dm_sba_tl_access	12103203198783199765493479329608502065660478103790376312136195222493858451626	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23850
	rv_dm_bad_sba_tl_access	48266627653886456318225069304366578014600373835165207724431614967560594763651	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23824
	rv_dm_sba_tl_access	95779819272738854888485609831626675821063716520252698055739516060800834422254	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23823
	rv_dm_delayed_resp_sba_tl_access	74137339963279851262704244551462753465179401689558468798571903830445548963544	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23807
	rv_dm_bad_sba_tl_access	15948516530900555188699318541561654076351629758751505855625068265891123508270	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23881
	rv_dm_autoincr_sba_tl_access	30981394483689365538044833638509081152025166018754292177973963989753973789782	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23860
	rv_dm_sba_tl_access	98011830630891277283939483242240770868147255843227537940163295192771253405438	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23834
	rv_dm_bad_sba_tl_access	47666833514754075713234150570911061835080525895931717067228461073021828126154	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23958
	rv_dm_sba_tl_access	6231484025906118428459453550033837074510733961222170313396966323762607376908	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_bad_sba_tl_access	39200962123967065045575640107693746411685791434189373940206742865146430845107	120	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23736
	rv_dm_sba_tl_access	72952023749539370574112327341639706513644704629083277014858122820242356558233	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23875
	rv_dm_sba_tl_access	48763056595025054142558430949030430724763489561819436768937822886797018694446	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23819
	rv_dm_autoincr_sba_tl_access	5139916284588238345725220773004149674694299778058181133184552982869884405174	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23959
	rv_dm_sba_tl_access	8766234892977908844261168615340380613869834944709627651970644095836605200201	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23824
	rv_dm_sba_tl_access	67271327793463548391806993914257196794733574771907973398821108369665745243784	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10265
	rv_dm_sba_tl_access	91818591748531192091796937090638917783395644226949975522647668011178662184713	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23778
	rv_dm_bad_sba_tl_access	92642913409125195139374011942618131181183395153364493817904330095601864598366	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23746
	rv_dm_sba_tl_access	4772934414996896880786640071572087566542763060441020178393991939718184143380	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_sba_tl_access	46612168496781373866659774854464587808035890783390525803828346113577189410189	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23808
	rv_dm_autoincr_sba_tl_access	89309673135637708978809113905034094599555907162414478075525314045630718703487	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23782
	rv_dm_sba_tl_access	29174115633489026581681666580442442151842888281873475955226724720035513195974	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
	rv_dm_autoincr_sba_tl_access	1666254316228586631249281647420944181456189258335294457595063942858386053169	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23808
	rv_dm_sba_tl_access	8847128263792855652101870825848743181226239813602952479310275395913230928632	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23830
	rv_dm_sba_tl_access	23925467197713813856583347246608233093007981501437316721997102548366812517744	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23819
	rv_dm_sba_tl_access	81495986326463799427274521268741726214703764376817439744913532072694799438798	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23789
	rv_dm_bad_sba_tl_access	44709918968377397775739223585176168494091333421898239845648651295535573437346	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23903
	rv_dm_autoincr_sba_tl_access	60200714871158989158766085379419801074485753448514812888206566894441419273133	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23989
	rv_dm_sba_tl_access	68204359006499129771817622417719078368110895782439613458592306444248273254870	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23866
	rv_dm_bad_sba_tl_access	35245961276653347725195769349495126748872018189786690688714488883019156623078	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23772
	rv_dm_sba_tl_access	106942937042193788540226957982890820454043487716140386242804712171502230459850	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23809
	rv_dm_bad_sba_tl_access	4511410814033841205021165761837148209709689413757400122809638187592570938187	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23826
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				36 test runs
	rv_dm_delayed_resp_sba_tl_access	56136902208824671645692225903464969409926028816797153601290146414765613297879	107	UVM_INFO @ 344108037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	102469741009895072369301421628905443505419627154437632798643382465022508064100	107	UVM_INFO @ 348102533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	60025873888898133387967906350451918791190942133155759448469510430259831873873	107	UVM_INFO @ 891864838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	89397156965587799862883582381948142037089983485536372096164497589668543139697	107	UVM_INFO @ 1260050091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	65406831564692828468056243163704168847771364378029509465802162630579483710977	107	UVM_INFO @ 275191326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	90641973411229760646086338624153603486722005336565629037786499863025436605190	107	UVM_INFO @ 296534576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	112986330532346774825735268651714401258191813603452511150298847363852873980080	107	UVM_INFO @ 66331054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	94473514057386722653223702341624411338441021531996421983250759660631888397551	107	UVM_INFO @ 118531324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	69023273214327260136651521341657240789970145270054945846129390832519752098114	107	UVM_INFO @ 388707152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	1585591623673541187612596994506496624294320985325966839750375180695460817984	107	UVM_INFO @ 181725013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	112677423653509074289050665809292974152769286881742224378582628880231254276193	122	UVM_INFO @ 13481554263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	22544809278148385265179763372968823183317713803294130268490072342054779200839	107	UVM_INFO @ 129634396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	106571984133061720457414901736520491958127984757297514641415723535377230517975	107	UVM_INFO @ 91708691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	83825876030784995033507942277719760128327316505960605152226835698576611984053	107	UVM_INFO @ 254766819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	94719464697025713952853346906367185016224508760087048045516670935385753162399	107	UVM_INFO @ 88815209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	25059963660882086709998983955997956182289965372035277005715620407936648798407	107	UVM_INFO @ 404153949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	39276939090515514912408005675902685389565587323353398610108131417534670718372	107	UVM_INFO @ 515494904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	79509054625858693584825707803412760168233520229422218862645265195588071527511	107	UVM_INFO @ 179329680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	2551304482266312694993403304679403122856183850041172553095668027625488057952	107	UVM_INFO @ 69920181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	59679119285141367744400523289974492793820641465536097591120169869050446466449	107	UVM_INFO @ 508931132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	32149594678081729035241158189408725058754291314674555973389956188239988494397	107	UVM_INFO @ 147621800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	75602357066070678221652135111602624941942694530666861896281273309754399774468	107	UVM_INFO @ 122522290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	35176275636185407431068764808150867036234795936945681084018102237293907374322	107	UVM_INFO @ 131803182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	45759008551600852009820163213896941094198914689969360483732586794278586562775	107	UVM_INFO @ 173051113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	9977122816688550506957773060894059175914461018025005157289323249363127942836	107	UVM_INFO @ 116793489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	24793952346976271386839496429302667256115391596556220098695874146995280278887	107	UVM_INFO @ 460956761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	93195105615678593912398533351128900320957738623915161326714142324947231586882	107	UVM_INFO @ 138353659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	40469419512123877785299995124714604402969680889502829647725288057270542715842	107	UVM_INFO @ 116290637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	107447304061483201817589648409514496870543505725787945446752951752542583234970	107	UVM_INFO @ 590992218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	7559620888094336407260363559053460864408860265424018835118957673760806909679	107	UVM_INFO @ 78183571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	61608726160123620848572802003438591753611317924621187571969822363071229720819	107	UVM_INFO @ 379505319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	6248458475994035466095882143991182267735218530291055111791319004567943689771	107	UVM_INFO @ 69344017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	92420520916100371703279722055680139363779110175745511954428673322642821976192	107	UVM_INFO @ 102219770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	97837197994063769416515863586882152400792208746189596709923130173900973619042	107	UVM_INFO @ 375878493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	42814734500792335805445922943051248606411814774010066459025874678813259160882	107	UVM_INFO @ 43123401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	82469116758906313462782077287449650396221515079178481509274040317978447972917	107	UVM_INFO @ 48225199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				16 test runs
	rv_dm_hart_unavail	54409930158114612727676075924867262656843049498598230507463524197951697588480	87	UVM_INFO @ 74387597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	16388797510258081087221982801801573439984785964015241706485792349712971463195	87	UVM_INFO @ 58604543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	106059906590944748278640493678123022698537027195235755872827073347382303194775	87	UVM_INFO @ 164770400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	48526688243083236558317604326849055916810528758553991945534958313295541435152	87	UVM_INFO @ 83661607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	114880179926644933032479359664725662291791992737470284331389363555741190616902	89	UVM_INFO @ 297093063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	95522235134410883676231623354387588572226114063101241013646526231877450945688	120	UVM_INFO @ 2780302907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	21783549151528720375965383125916269379724087529520454838416724182002424063051	87	UVM_INFO @ 137869557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	45457482603912293952264556749524450193147711922732895645433438603552979908416	88	UVM_INFO @ 272017902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	107868166951721227859063930080820829833229650417412468558238355241087581371502	91	UVM_INFO @ 76184211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	69921017049211816125227939732415868230433400817553676665220832579311027461134	88	UVM_INFO @ 163591305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	5997227561994309179455467994155077832112611065585951381112950858274062312512	139	UVM_INFO @ 1433462174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	74573192608895473664361732726794831785797982517840976291811741062828761653020	97	UVM_INFO @ 577264559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	93326563104421164747540635091402175639590169618970392959693131608115373928342	91	UVM_INFO @ 1145225642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	80472544812667621030873854426107686117134315360505732378001369773409596122978	115	UVM_INFO @ 1853669009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	35364477518485958921101926662037394174615542223304263793087180192913255987933	90	UVM_INFO @ 648797054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	10388685697051873635655733845102547888078158234453601934101774979505220817528	92	UVM_INFO @ 1378022769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				13 test runs
	rv_dm_jtag_dmi_debug_disabled	104728313496079681607718425435823174146697499068126431796331110677211294185111	87	UVM_INFO @ 203116749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	49583049115568646844511680487397199869726312562927046050967697415847150290100	88	UVM_INFO @ 146719607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	55104212911703569574081771073254652065043919745896063610100823456115196009090	87	UVM_INFO @ 252813538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	77614169860996751721131177753642828441253852477565423204232284095883780136559	126	UVM_INFO @ 5908290935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	27216092637527313920251724830855429706170169620920219750311505146526277199509	107	UVM_INFO @ 2687807442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	104668291788449789847172750494024098871298702142151031971388993051936968344067	125	UVM_INFO @ 6341949325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	11131912134945773204251230281371095716248319212640828495513488605656376719626	89	UVM_INFO @ 755881458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	18905946403016557228580603405106812498727478703439201759153838010208419569984	90	UVM_INFO @ 1268561651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	57622883606214688709471429911871271161861353996868812861309622382075740596489	141	UVM_INFO @ 2547530422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	97980303311774521365493377286553474265282411909905103393584885594282903958461	92	UVM_INFO @ 2036610751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	60426643050976332720258994911310991076781613202077514347888503733492245923779	106	UVM_INFO @ 808396443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	111952728058313995573221877595996981350984924705335722734679619300973555364449	92	UVM_INFO @ 5288069095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	75372231385052898891037480342116866019503303974524833738547258853600235725644	106	UVM_INFO @ 2737800231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				12 test runs
	rv_dm_mem_tl_access_resuming	31218378390192465254134259905426670019414326818342827530698845471817975798661	87	UVM_INFO @ 183861578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	53739479614567656456089328921931324478113030221409408145078676416557759496078	127	UVM_INFO @ 2103396875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	93602801118207448262226628900961414576639267159254385729701182480652976822641	87	UVM_INFO @ 125433230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	53247245911482554778258495026015428079945873689159520980949370775516556081016	90	UVM_INFO @ 1141565986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	53557824714356982080775550234583318612345372294755079621140439106725205554794	96	UVM_INFO @ 2868193789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	108245292230044165550263247652205203204987566968583998202518838484342169352133	139	UVM_INFO @ 7282697812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	17440875308436525457897868875031025462276466225326400979025986576686378639184	88	UVM_INFO @ 430597473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	106697157113862093767732558070591636537509886292374368067552417524159861769452	144	UVM_INFO @ 2698044120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	70606716315809465283912398596647132839663424029302247969364697663684122112793	113	UVM_INFO @ 921645501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	54695745244458715568006389669638306786200780697078723145460329509577230956328	97	UVM_INFO @ 466397710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	24306094920674517519841597238730747552805344820524236430162231700924575868142	90	UVM_INFO @ 806837470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	52552174382376439569341017934189802694632560491550970657468430134493917301583	88	UVM_INFO @ 181693663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				4 test runs
	rv_dm_buffered_enable	101356575678049709416941262651184630649139718099392360148379572392460196077013	91	UVM_INFO @ 224641479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	23888013392728785842173776300949749590551634871799308215158104864055100834573	90	UVM_INFO @ 581366385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	94209875626009527367522096294914174719782868131916789922978067330431949195493	90	UVM_INFO @ 623502366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	107066730812996382989304650178450196720953647252721104072379167404424548597643	90	UVM_INFO @ 165244685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	rv_dm_stress_all	70243291353349756640374326179020911743803715275104396113493212506394207447320	None
	rv_dm_stress_all	30380567691083287896774953699568118695569218198794383569101697182936529955236	None
	rv_dm_stress_all	96850646701901788982936560052675960970997184997309914655564808857371807880787	None
UVM_FATAL (cip_base_vseq.sv:1230) [rv_dm_common_vseq] Check failed (vseq_done)				3 test runs
	rv_dm_stress_all_with_rand_reset	30371913956354019795772721316661417377555835657421350671836734595712972172540	95	UVM_INFO @ 1562077639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	66481715833715415869524732259384616042350401222310352871952460566014495890527	121	UVM_INFO @ 4431414175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	114939172708659839973847265413978050062084332865899663519122847405135391558032	112	UVM_INFO @ 1186687439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	72316583918879759724144563329696085594997418865551400511716160427615450572195	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	26538650995318222218673938084750409109576765678453408522246275189855197132319	91	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23888) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	32675342632263450070477925125134516751210928291768432206648351395148260196367	87	). UVM_INFO @ 108490060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23858) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	12221626677973992930137371936867486002010675335782742358603993043784325045259	87	). UVM_INFO @ 32861159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---