Simulation Results: rv_timer

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.29 %
  • code
  • 90.45 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.000s 290.873us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 64.678us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 2.000s 17.123us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 739.033us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 98.597us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 45.742us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 2.000s 17.123us 5 5 100.00
rv_timer_csr_aliasing 1.000s 98.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 20 20 100.00
rv_timer_random_reset 6.000s 4644.915us 20 20 100.00
disabled 20 20 100.00
rv_timer_disabled 5.000s 2121.347us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 418.000s 1100961.522us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 418.000s 1100961.522us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 10.000s 8262.644us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 52.165us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 2.000s 23.167us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 4.000s 746.555us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 4.000s 746.555us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 64.678us 1 1 100.00
rv_timer_csr_rw 2.000s 17.123us 5 5 100.00
rv_timer_csr_aliasing 1.000s 98.597us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 17.362us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 64.678us 1 1 100.00
rv_timer_csr_rw 2.000s 17.123us 5 5 100.00
rv_timer_csr_aliasing 1.000s 98.597us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 17.362us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 2.000s 418.181us 5 5 100.00
rv_timer_tl_intg_err 2.000s 163.538us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 163.538us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 3 10 30.00
rv_timer_min 2.000s 213.339us 3 10 30.00
max_value 1 10 10.00
rv_timer_max 3.000s 288.954us 1 10 10.00
stress_all_with_rand_reset 20 20 100.00
rv_timer_stress_all_with_rand_reset 59.000s 21358.378us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 52620882346881787464020294678789775953124362696439010319619515708160548739764 84
UVM_INFO @ 288953935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 63155359080651680082150160033218877446140987858670814667980838691122220301495 84
UVM_INFO @ 597583291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 6480944180527084105148706056925746643050635521883582972047299178701414140192 84
UVM_INFO @ 43103133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 87516582764896739372293253979001054727893450168389575478339437577859181212422 84
UVM_INFO @ 86644796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 63264369072397932320979036636131074756385735063019842858572986716428885305556 84
UVM_INFO @ 48590610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 36675891129709442120572334618175310050953381299328433770794359149005226311163 84
UVM_INFO @ 167814313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 25807180371132042914749741692194156158074936694577547492516066998525776410020 85
UVM_INFO @ 183945817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 46507040103049054897545029389101369826093210637842912231424016459453948175612 84
UVM_INFO @ 475039950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 3415496065091462767606322447065308657544614270261811074304105449185433829599 84
UVM_INFO @ 43180792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 7 test runs
rv_timer_min 59568002582371076427341374789562408276532820453776016589861032405424842454493 85
UVM_INFO @ 76825435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 12026840442481877903479498980481000603664293745673568510289500821904711577794 84
UVM_INFO @ 213339051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 21320931846708728086381874640253615009559506786486252035044058941334701470781 84
UVM_INFO @ 223871411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 56241245787568069960550027621506991903145698515175350691921558359794305801632 88
UVM_INFO @ 263975268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 4992094698521860118416686893717999805388283577135330098699699073301086689373 84
UVM_INFO @ 379507290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 14424115707360853995506620709687751368160782744811643960711182777596064334614 84
UVM_INFO @ 65057260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 23792500023405258378400704927698122734253217944339810732262712562491620884104 84
UVM_INFO @ 79505479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---