Simulation Results: spi_host

 
14/08/2026 15:00:29 DVSim: v1.49.0 sha: d3fa90d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.88 %
  • code
  • 91.30 %
  • assert
  • 96.60 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 53.000s 1947.567us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 18.347us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 1.000s 151.334us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 165.537us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 101.552us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 132.811us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 1.000s 151.334us 5 5 100.00
spi_host_csr_aliasing 1.000s 101.552us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 21.726us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 21.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 59.820us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 18.000s 1339.506us 10 10 100.00
spi_host_error_cmd 2.000s 109.007us 10 10 100.00
spi_host_event 56.000s 2164.044us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 5.000s 1050.439us 10 10 100.00
speed 10 10 100.00
spi_host_speed 5.000s 1050.439us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 5.000s 1050.439us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 722.000s 43770.924us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 54.000s 1405.422us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 23.922us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 5.000s 1050.439us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 5.000s 1050.439us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 53.000s 1947.567us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 53.000s 1947.567us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 110.000s 16216.881us 10 10 100.00
spien 10 10 100.00
spi_host_spien 322.000s 52333.767us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 145.000s 31393.909us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 9.000s 3430.392us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 18.000s 1339.506us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 39.876us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 16.191us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 3.000s 421.994us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 3.000s 421.994us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 18.347us 1 1 100.00
spi_host_csr_rw 1.000s 151.334us 5 5 100.00
spi_host_csr_aliasing 1.000s 101.552us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 34.035us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 18.347us 1 1 100.00
spi_host_csr_rw 1.000s 151.334us 5 5 100.00
spi_host_csr_aliasing 1.000s 101.552us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 34.035us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 403.750us 25 25 100.00
spi_host_sec_cm 2.000s 525.581us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 403.750us 25 25 100.00