Simulation Results: ac_range_check

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.30 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.63 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
96.23%
V2
98.86%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 49.000s 1708.194us 20 20 100.00
ac_range_check_smoke_racl 18 20 90.00
ac_range_check_smoke_racl 69.000s 5512.105us 18 20 90.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 691.782us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 217.780us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 46.000s 10536.421us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 25.000s 1180.390us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 199.526us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 217.780us 5 5 100.00
ac_range_check_csr_aliasing 25.000s 1180.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 65.797us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 30.000s 512.918us 1 1 100.00
stress_all 9 10 90.00
ac_range_check_stress_all 381.000s 24897.509us 9 10 90.00
alert_test 10 10 100.00
ac_range_check_alert_test 31.000s 26.818us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 3.000s 15.379us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 5.000s 473.607us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 5.000s 473.607us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 691.782us 1 1 100.00
ac_range_check_csr_rw 3.000s 217.780us 5 5 100.00
ac_range_check_csr_aliasing 25.000s 1180.390us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 629.623us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 691.782us 1 1 100.00
ac_range_check_csr_rw 3.000s 217.780us 5 5 100.00
ac_range_check_csr_aliasing 25.000s 1180.390us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 629.623us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 22.000s 4276.209us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 22.000s 4276.209us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 22.000s 4276.209us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 22.000s 4276.209us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 117.000s 21066.311us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 33.455us 5 5 100.00
ac_range_check_tl_intg_err 13.000s 820.642us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 429.000s 11964.075us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 40.000s 1465.017us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:373) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 3 test runs
ac_range_check_stress_all 56722311272310113565969911451705225109006559208210109222933713793449464814979 13251
UVM_INFO @ 28026060431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 106229642088010790250806850962629281386836273662555628603859424693188260422051 4330
UVM_INFO @ 41771928124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 80545790838363894326888700776167125811974916896901094583740759712778028517193 4240
UVM_INFO @ 1874685578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---