Simulation Results

Simulation Results: clkmgr

21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
78.44 %

code
70.02 %

assert
90.50 %

func
74.80 %

line
82.37 %

branch
87.53 %

cond
80.22 %

toggle
100.00 %

FSM
0.00 %

Validation stages

V1		65.22%
V2		69.23%
V2S		28.57%
V3		0.00%

15/23 passed

65.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.390s	94.582us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.350s	33.622us	1	1	100.00
csr_rw				3	5	60.00
	clkmgr_csr_rw	1.520s	47.527us	3	5	60.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	4.820s	167.386us	0	1	0.00
csr_aliasing				0	1	0.00
	clkmgr_csr_aliasing	1.650s	40.976us	0	1	0.00
csr_mem_rw_with_rand_reset				1	5	20.00
	clkmgr_csr_mem_rw_with_rand_reset	2.390s	84.743us	1	5	20.00
regwen_csr_and_corresponding_lockable_csr				3	6	50.00
	clkmgr_csr_rw	1.520s	47.527us	3	5	60.00
	clkmgr_csr_aliasing	1.650s	40.976us	0	1	0.00

81/117 passed

69.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	4.120s	231.349us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	2.550s	109.149us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.790s	74.692us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.390s	94.582us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.150s	14.262us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.260s	33.134us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.150s	14.262us	0	10	0.00
stress_all				1	10	10.00
	clkmgr_stress_all	3.750s	373.031us	1	10	10.00
alert_test				10	10	100.00
	clkmgr_alert_test	2.140s	84.274us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	12.240s	846.007us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	12.240s	846.007us	25	25	100.00
tl_d_outstanding_access				5	12	41.67
	clkmgr_csr_hw_reset	1.350s	33.622us	1	1	100.00
	clkmgr_csr_rw	1.520s	47.527us	3	5	60.00
	clkmgr_csr_aliasing	1.650s	40.976us	0	1	0.00
	clkmgr_same_csr_outstanding	1.360s	25.869us	1	5	20.00
tl_d_partial_access				5	12	41.67
	clkmgr_csr_hw_reset	1.350s	33.622us	1	1	100.00
	clkmgr_csr_rw	1.520s	47.527us	3	5	60.00
	clkmgr_csr_aliasing	1.650s	40.976us	0	1	0.00
	clkmgr_same_csr_outstanding	1.360s	25.869us	1	5	20.00

V2S

30/105 passed

28.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				1	30	3.33
	clkmgr_sec_cm	170.510s	10022.187us	1	5	20.00
	clkmgr_tl_intg_err	2.210s	74.879us	0	25	0.00
shadow_reg_update_error				16	20	80.00
	clkmgr_shadow_reg_errors	2843.830s	200000.000us	16	20	80.00
shadow_reg_read_clear_staged_value				16	20	80.00
	clkmgr_shadow_reg_errors	2843.830s	200000.000us	16	20	80.00
shadow_reg_storage_error				16	20	80.00
	clkmgr_shadow_reg_errors	2843.830s	200000.000us	16	20	80.00
shadowed_reset_glitch				16	20	80.00
	clkmgr_shadow_reg_errors	2843.830s	200000.000us	16	20	80.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.960s	63.856us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	2.210s	74.879us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.150s	14.262us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.260s	33.134us	0	10	0.00
sec_cm_meas_config_shadow				16	20	80.00
	clkmgr_shadow_reg_errors	2843.830s	200000.000us	16	20	80.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	5.630s	320.300us	10	10	100.00
sec_cm_jitter_config_mubi				3	5	60.00
	clkmgr_csr_rw	1.520s	47.527us	3	5	60.00
sec_cm_idle_ctr_redun				1	5	20.00
	clkmgr_sec_cm	170.510s	10022.187us	1	5	20.00
sec_cm_meas_config_regwen				3	5	60.00
	clkmgr_csr_rw	1.520s	47.527us	3	5	60.00
sec_cm_clk_ctrl_config_regwen				3	5	60.00
	clkmgr_csr_rw	1.520s	47.527us	3	5	60.00
prim_count_check				1	5	20.00
	clkmgr_sec_cm	170.510s	10022.187us	1	5	20.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.600s	30.563us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	36.180s	1615.076us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				27 test runs
	clkmgr_tl_intg_err	68994891666053853857438953180975501764845722102838549455585323071672858247244	81	UVM_INFO @ 1366669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	5727815978956248397386619755417749005165054946429111530752441397240675113189	81	UVM_INFO @ 5712152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	79842542397639085000553183780518719488256937745454534012589208662623988365187	97	UVM_INFO @ 10887452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	61011529512407875441527569699298246177359288972512016923515066541493737605792	82	UVM_INFO @ 4887459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	36932359320698882161975569725847616478733655289351319601275242513270204328377	88	UVM_INFO @ 57273214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	79284672241983764845824208320334557834317301341964302485597655442978191663541	81	UVM_INFO @ 11545179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	16839322572023211489618440903435981188245136076844734354205689459609016556093	81	UVM_INFO @ 63856350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	51112434700991243195140963201730541914828852883278915966386346823029491164950	91	UVM_INFO @ 5445181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	60605553367485287711590563743830625931125190670283965231606034067221224678764	82	UVM_INFO @ 20722064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	86683835760729021581750670811077612230981508569861115794438574452037612779853	88	UVM_INFO @ 5787560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	13211589180330176749000111685014556152464868819612614581700119717862710733478	81	UVM_INFO @ 2677595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	28113763749512375268537981310337688165432485685014476135741404540153820791462	81	UVM_INFO @ 10771685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	96017918558638658672846259119186004490366766040934198109438625125575760323122	91	UVM_INFO @ 41070386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	70288788482818338839705422841141318564778348382340703782806430719284104729527	81	UVM_INFO @ 6296170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	114867298271034030133925782153187975361191299336335745471282960619670668716097	93	UVM_INFO @ 23113203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	37470986601894780361610870430444223859493862817384326973488163260572300625869	81	UVM_INFO @ 11127319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	56689181880052054383090961569594098649105584126200165309804417625744851054543	81	UVM_INFO @ 3566585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	52238916944143077020938220562230949093098161125546836132911832799694651189666	81	UVM_INFO @ 60603434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	63302990860041706467144279549946704256351298151995788867156348272113271470405	88	UVM_INFO @ 5437076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	96199693285325592672206280551698010147343114144981109479241311867270092430150	111	UVM_INFO @ 36403456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	15456473317481689223028831453777136552337322723568330112920427883335032790906	81	UVM_INFO @ 2747347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	38815685018977897805272841110315433485992909269037629264978454203520398042666	81	UVM_INFO @ 5779215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	107491168883130008075453966040902617537888974477185185406190130913522852799943	92	UVM_INFO @ 6334049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	90054979294318084143116779031200821593258173983204809455685795054396490898101	84	UVM_INFO @ 14269874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	81405022340844343434551061505161442392116673185416075616695486327608211413451	88	UVM_INFO @ 43595811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	80305339250030359511510922680711446071433251082872485866745605290257884612079	81	UVM_INFO @ 1799456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	8087288674686407350599761683034015288732435522368192751316569890927770336616	99	UVM_INFO @ 12080984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				25 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	75751760796569345683819591203395075835947529678998822995505879302087795646813	81	UVM_INFO @ 8475888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	32689917057297012318064287636755862712005919313339420922087389814717518570356	81	UVM_INFO @ 2677393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_aliasing	7444339149155560439182145944585920123883975679121864749970940941306328599628	81	UVM_INFO @ 40975872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	55525340310856496475464126538086683202123425111789251281726191551106275541990	81	UVM_INFO @ 4788746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	17215483833670293049579074567494884420823990451627334497319187452088567970834	82	UVM_INFO @ 21317346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	94622231233701690295642760049293622864123784793578471972612341990766726627965	81	UVM_INFO @ 10509185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	441347657877805545735429608041741634921477739787655089971872392797268125475	84	UVM_INFO @ 9703507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	56465729425566016695329945940731003704519929726930833151252867980973584831341	82	UVM_INFO @ 2753412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	89131890995477551952622561430220674849009625441280699181414755745604571106521	81	UVM_INFO @ 13350049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	113445412801477501624832298792016144235967590264490884478436193637307112537019	81	UVM_INFO @ 31246922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	73144755384478239405644973720109676761786723572946470661501590808450342470233	81	UVM_INFO @ 2598068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	58511071027798573504065470415056429313648278867321488790503011542863959332954	81	UVM_INFO @ 9923060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	7137501898139952159444648483457905057064838720140895187776949915643294913181	107	UVM_INFO @ 42549912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	73527440202000882413188634302945637938207999817711080770759657287050433173385	81	UVM_INFO @ 5390062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	77493143653141436391678748708648288605791000430090311246197043662915520949284	110	UVM_INFO @ 26681262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	115354551400334491813146094285187094135905951872502614494989340773940149234396	81	UVM_INFO @ 5684333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	111593854908389131932664214801890571605799314919014501314698370000975203127818	81	UVM_INFO @ 16592902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	84702535722413561420233820002959754186930538548635405930658345033266551828673	84	UVM_INFO @ 2832646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	50743377255473188877278354392663884417363575590788870913935395478995787987963	81	UVM_INFO @ 3516760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	72332997079233325915217636620716060936148209689946713670579210357438374412766	118	UVM_INFO @ 61497717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	113633008073423452353769173028063673313093817640775715253780037069184690664625	81	UVM_INFO @ 13011262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	31390619319969990600747826533490413806403360153419230755075531867120710380474	81	UVM_INFO @ 28139154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	51079060100632473891638225586957991634372229903268691842968722766451527226040	91	UVM_INFO @ 7161983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	81797773176618221973606839059839354686773980211321585802682003038641936805579	81	UVM_INFO @ 3506388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	23348017140076636929932385942282985399763250850525944814910097038802357026914	108	UVM_INFO @ 74878870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				21 test runs
	clkmgr_frequency	40948245988342077776758161397592241210905120745365009609158823562887141764888	82	UVM_INFO @ 4061224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	101119945907955747833225363241886994215787786303194406946796463984992012365473	81	UVM_INFO @ 17704921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	85828451180442314023627828137771659505978640441064746239328919217659935881317	122	UVM_INFO @ 41649808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	15629912325858373004641821805393943419022088893893137775579954265868428583221	84	UVM_INFO @ 10328171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	104532896860441394947702633343689899753767039627470878327989579760462659212795	83	UVM_INFO @ 136868522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	46361782867986144039741364770703122598230744792007485776398139142368478279216	81	UVM_INFO @ 7845813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	32246115877950381819511814016961352413093976362953175565773986365589833472684	259	UVM_INFO @ 1615075618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	102595130967406106050640782172680466667716279709912099705816262658561266537198	82	UVM_INFO @ 5483177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	47464178058491413905821595604975078895237223076211254801882465103649816645394	81	UVM_INFO @ 9004056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	68565632425272617667333766831434261652255477357876664173310235567796977182308	84	UVM_INFO @ 6070492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	1394954527098493489168017758854314498352768528769831273472617718622107196816	87	UVM_INFO @ 18787700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	75666645128287685419497211691315851736246272254295738888245707625868881685946	88	UVM_INFO @ 10137464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	4981768263088181439791598846924870356570336376557083656751837371444034890476	84	UVM_INFO @ 12306939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	52963242482166406149395965696611839612379212458181393084496348143166380213312	82	UVM_INFO @ 121073707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	17936238475195519948775366538071416682912635638283165836080512392691121176812	82	UVM_INFO @ 6691875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	59865046610943004045774442728071534512438598572808430863887448855172922019647	84	UVM_INFO @ 11665816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	83964081344905490754244556125970433632479710262354416422196682808356780044457	82	UVM_INFO @ 12826281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	39923318180437393346417534702331362439975535866918095869918530522305852016275	82	UVM_INFO @ 6356913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	115757024152607061930604914573284829614652164396993103622982581525698974827150	83	UVM_INFO @ 43179318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	55994952051109498358769652799887477614579896762210339352181666740191462514928	81	UVM_INFO @ 14262268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	37153102479845300750775505374006222681109641081932655764223104197040332287359	170	UVM_INFO @ 373030742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				18 test runs
	clkmgr_frequency_timeout	25027985043089246583063704601761121450350678465928547048171448513514751004721	84	UVM_INFO @ 14870194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	31103299019972097952009590286395405492592641886083885178488485670400192508872	85	UVM_INFO @ 204855921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	83762404852138774857072905418366504598505844711046991112213298479659740833442	83	UVM_INFO @ 2370355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	35384402671129481671606068525487969994047892662556097138535682119378519353076	85	UVM_INFO @ 6258736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	78652842041826567867590568394018232826055024697412970601911915922922526136164	84	UVM_INFO @ 1669348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	44062227390913414971618329012492295372188267479189449557628609101254404750062	132	UVM_INFO @ 48714964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	67858569560413605668350624131587853344547245144966560273748634730983811400955	84	UVM_INFO @ 3072756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	99129572636840232302963316395898530937707178553223454122479317425339904061926	148	UVM_INFO @ 134451371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	86615533539722483519227707716608837376318045129295954672351323800520254630945	84	UVM_INFO @ 6710661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	95297021864730148038739462226489343689552292536351043908077034008759522766232	85	UVM_INFO @ 12721551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	105456571025951991594995606253916033405851563146356043981579480298079776865783	84	UVM_INFO @ 12893281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	74510343127385319619960355554059507373532214230859472615803451743585796480764	84	UVM_INFO @ 15844020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	95031430489324567899279294334068522882145863017066624780729867073221193390234	84	UVM_INFO @ 3672904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	8126200554276230350395748963321095270448851687108804338239262205941778191926	84	UVM_INFO @ 9344414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	36741576494574299920584841809087699957654498694448096913837841380778344245534	84	UVM_INFO @ 33134232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	49489051661555563688112359341249282106441094056945675823904962744988470391101	139	UVM_INFO @ 86445422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	8257506145839551391916897981843036943108766602812514018462359484268331607416	83	UVM_INFO @ 3969265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	42075652935142569329942886953974158123690398060866696284508553144426663910609	85	UVM_INFO @ 112667034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				8 test runs
	clkmgr_regwen	68926833038949967048916917421409723391695193744460952031475752699682678270884	80	UVM_INFO @ 2232403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	4413677150739475102789546577319110849180620572085688209831648794275773731294	80	UVM_INFO @ 4621454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	90984375677808619717876527869727205812940631367279754516569061531870700872982	80	UVM_INFO @ 4596858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	90099768451187958743838699712147973701618093578334331036199652245007999910934	80	UVM_INFO @ 2625453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	44837637310658727153931553890552703901390366136519585881672100386110544024410	80	UVM_INFO @ 3177130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	40341824882448507956357437034195084770470488539785483253242030869179681488510	80	UVM_INFO @ 30562884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	66291114370308076800691682336471497570953218903196891411336312301070452082903	80	UVM_INFO @ 7727806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	32139798920781688627783606431145256297578151006995470671533515848245126220260	80	UVM_INFO @ 3607775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1087) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				4 test runs
	clkmgr_sec_cm	21610519537726635383628699405973637275917565873146428941803758555679398526178	104	UVM_INFO @ 10022186548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	9273143525844759099869645580991159269559234267950826279883599717523359242151	86	UVM_INFO @ 10015129933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	60139350924172887946816663339549771122643879430272108711300620577489220962518	125	UVM_INFO @ 10167778418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	90370866491503945187118530900571631610396221438751568142242226840881698051860	122	UVM_INFO @ 10062589324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				4 test runs
	clkmgr_same_csr_outstanding	60732037493646875821015152859106407247597346124003089948473104335287921819910	81	UVM_INFO @ 2897209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	73511094996970440828850292018593427335099856229911380468528806917747303617584	81	UVM_INFO @ 16260761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	113265000379586325545600361370174416346354000904113464868528682534478994675725	81	UVM_INFO @ 15219998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	30238904058356289268700393597719993424554814742517486618521309747600840804637	81	UVM_INFO @ 2810163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				4 test runs
	clkmgr_shadow_reg_errors	9574967939125100004818062148661160279082583488230116246954091857003052509649	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	52729998603307309597944729955540090270287709721531872261150362838094313940117	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	100982303847066901944374841533643002816459063304041077170319369064962776954912	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	110522763919205661047365655562294337587777194704598115595965122088252943606036	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				2 test runs
	clkmgr_regwen	37375146816076002989508168727860860108995007168033466037153962662551488237383	80	UVM_INFO @ 4829329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	11776103989954124260808301335347891567282215756180942051985489823697058867633	80	UVM_INFO @ 8913753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	59004694325062973437027204356384768648952981578908072275857277430152933269786	81	UVM_INFO @ 167386182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---