Simulation Results: csrng

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.61 %
  • code
  • 96.17 %
  • assert
  • 97.16 %
  • func
  • 90.50 %
  • block
  • 98.49 %
  • line
  • 99.50 %
  • branch
  • 96.30 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.39%
V2S
99.84%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 5.000s 161.147us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 16.353us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 4.000s 114.693us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 27.000s 1047.724us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 8.000s 302.408us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 4.000s 57.435us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 4.000s 114.693us 5 5 100.00
csrng_csr_aliasing 8.000s 302.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
alerts 500 500 100.00
csrng_alert 62.000s 3366.454us 500 500 100.00
err 500 500 100.00
csrng_err 7.000s 20.596us 500 500 100.00
cmds 6 25 24.00
csrng_cmds 387.000s 15973.952us 6 25 24.00
life cycle 6 25 24.00
csrng_cmds 387.000s 15973.952us 6 25 24.00
stress_all 23 25 92.00
csrng_stress_all 1847.000s 104788.468us 23 25 92.00
intr_test 10 10 100.00
csrng_intr_test 3.000s 16.750us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 6.000s 51.347us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 14.000s 346.534us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 14.000s 346.534us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 3.000s 16.353us 1 1 100.00
csrng_csr_rw 4.000s 114.693us 5 5 100.00
csrng_csr_aliasing 8.000s 302.408us 1 1 100.00
csrng_same_csr_outstanding 4.000s 144.899us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 3.000s 16.353us 1 1 100.00
csrng_csr_rw 4.000s 114.693us 5 5 100.00
csrng_csr_aliasing 8.000s 302.408us 1 1 100.00
csrng_same_csr_outstanding 4.000s 144.899us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 6.000s 255.786us 5 5 100.00
csrng_tl_intg_err 16.000s 1054.786us 25 25 100.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 4.000s 141.307us 25 25 100.00
csrng_csr_rw 4.000s 114.693us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 62.000s 3366.454us 500 500 100.00
sec_cm_intersig_mubi 23 25 92.00
csrng_stress_all 1847.000s 104788.468us 23 25 92.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
csrng_sec_cm 6.000s 255.786us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
csrng_sec_cm 6.000s 255.786us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
csrng_sec_cm 6.000s 255.786us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
csrng_sec_cm 6.000s 255.786us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
csrng_sec_cm 6.000s 255.786us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 62.000s 3366.454us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
sec_cm_constants_lc_gated 23 25 92.00
csrng_stress_all 1847.000s 104788.468us 23 25 92.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 62.000s 3366.454us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 16.000s 1054.786us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
csrng_sec_cm 6.000s 255.786us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
csrng_sec_cm 6.000s 255.786us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 23.000s 1270.231us 200 200 100.00
csrng_err 7.000s 20.596us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:667) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 18 test runs
csrng_cmds 43293782544814507772343082647491989289134144166361437709776253302286938539081 100
UVM_INFO @ 29410358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 80832005909521164542543523728127140288847074198048210602765832593193243730648 100
UVM_INFO @ 154235115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103672820852523981250171864493928321704314875110494654276382586258187313365324 100
UVM_INFO @ 1115696685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 42967152837932486446403229875219003928685753877147254177241463363470504881324 100
UVM_INFO @ 94566249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 96038928675977155447229314402840569374883436331533755608006098202865634457751 100
UVM_INFO @ 564361264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 12560674786533457328111497148361827715650678687249482370377805941781395080742 100
UVM_INFO @ 145269139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 105820983932865631145465828044792398165533271882933924789688783116994887444133 100
UVM_INFO @ 86142704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 108482206307053105314761691713279164439920670240404953327394747695423096473137 110
UVM_INFO @ 365595184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 58835016441640866400304431075500010186877591930649339361628767582548601505802 100
UVM_INFO @ 284778161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 106121310283604951261365990285407580384009362267347165263744502800857909237320 100
UVM_INFO @ 86006643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 100387871155181047081962451691942285670680658771072216711824511188738649098905 100
UVM_INFO @ 217610885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 109265312840036350515423729030362216090433512416921325414335164861160161140858 100
UVM_INFO @ 118740209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 24978497157918373831278598366618991190312471013018584933390968508419847906199 100
UVM_INFO @ 753721133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 12348248418562137529899589079530189322581247527519920227612062327151457584572 100
UVM_INFO @ 168415327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 24467835532449398419953615535106036523902226345342153315518221841115675131475 100
UVM_INFO @ 422359505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 114176021513380424412450992647400698395193569044657471974807700573854049469373 100
UVM_INFO @ 359904244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 108107523506772985478848953395277353312120221309679596458369645872714428798371 100
UVM_INFO @ 88227297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 3594815580556571594431744413541940811258556433714926171371345829094427996127 100
UVM_INFO @ 53778707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 8 test runs
csrng_stress_all_with_rand_reset 43424922050924114399783841515118003715391015923948408547397357548657105033482 None
csrng_stress_all_with_rand_reset 115345454050259835136734327310588991428588714844344735105524910617242765313446 None
csrng_stress_all_with_rand_reset 57162504003422736761916432606406047393311986375492516692603145024163556443140 None
csrng_stress_all_with_rand_reset 49048571041438093902157816746273241204893959700716975024662656412259460913935 None
csrng_stress_all_with_rand_reset 84605843444252549365810411152696778303171431439698489107368605973235207601682 None
csrng_stress_all_with_rand_reset 12646708437359942716821083116619524905051518422575105284308598188090795179880 None
csrng_stress_all_with_rand_reset 86255890618563863216740716102006934124060026128527990664599971862032570455002 None
csrng_stress_all_with_rand_reset 51948673589127832943129074233628216269153483918660090861351816084629690679927 None
UVM_ERROR (csrng_scoreboard.sv:173) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 3 test runs
csrng_stress_all_with_rand_reset 82237978415038405633891298315248166051574992789955987376207913715703730386263 109
UVM_INFO @ 148492396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 89685471977883426526441198678476520715444277395356814534789566688132698788452 113
UVM_INFO @ 527825804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 89374549695709945497855411387040827776778286833899213351504794879881391593804 128
UVM_INFO @ 17415735312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:269) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 1 test run
csrng_cmds 23149890763206020916028498859133119682433037001370556388777815657209537301963 108
UVM_INFO @ 7074960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 67295849805247625788525869680533095063893757172531414792119728886591339341426 195
UVM_INFO @ 8641283543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---