Simulation Results: edn/edn0

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.24 %
  • code
  • 95.31 %
  • assert
  • 98.67 %
  • func
  • 58.74 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.31 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.35%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 2.000s 31.802us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 17.020us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 66.064us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 534.718us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 24.400us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 3.000s 57.028us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 66.064us 5 5 100.00
edn_csr_aliasing 2.000s 24.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 7.000s 58.933us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 7.000s 58.933us 100 100 100.00
genbits 100 100 100.00
edn_genbits 7.000s 58.933us 100 100 100.00
interrupts 20 20 100.00
edn_intr 2.000s 22.298us 20 20 100.00
alerts 200 200 100.00
edn_alert 7.000s 30.055us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 29.637us 100 100 100.00
disable 90 100 90.00
edn_disable 2.000s 17.191us 50 50 100.00
edn_disable_auto_req_mode 18.000s 500.000us 40 50 80.00
stress_all 30 30 100.00
edn_stress_all 7.000s 352.620us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 14.308us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 82.973us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.000s 1358.397us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.000s 1358.397us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 2.000s 17.020us 1 1 100.00
edn_csr_rw 2.000s 66.064us 5 5 100.00
edn_csr_aliasing 2.000s 24.400us 1 1 100.00
edn_same_csr_outstanding 2.000s 26.052us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 2.000s 17.020us 1 1 100.00
edn_csr_rw 2.000s 66.064us 5 5 100.00
edn_csr_aliasing 2.000s 24.400us 1 1 100.00
edn_same_csr_outstanding 2.000s 26.052us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 13.000s 1080.784us 5 5 100.00
edn_tl_intg_err 4.000s 350.997us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 111.787us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 7.000s 30.055us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 13.000s 1080.784us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 13.000s 1080.784us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 13.000s 1080.784us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 13.000s 1080.784us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 7.000s 30.055us 200 200 100.00
edn_sec_cm 13.000s 1080.784us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 7.000s 30.055us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.000s 350.997us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 30 90.00
edn_stress_all_with_rand_reset 141.000s 10940.216us 27 30 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 6 test runs
edn_disable_auto_req_mode 94949786875304788746324827342583576416455744109500309638212695678164294162569 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 20640862767206903277107235749526503298856214746992697370908210872642170604740 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 20655089916893654892499071620762042949325441159614841532030415125280290862743 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 40516824910675523677167193253165770117283547951858991047396512787498062423164 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 14191260705884595384206407748757743600518812449942897842639422874242434299811 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 24864896231634765810968909780406187243339899386202786845470696570216236812254 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 4 test runs
edn_disable_auto_req_mode 19735058699115285887120205437983793493910336034857311782650461604316135442107 103
UVM_INFO @ 301555482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 43821927002696634707101049804781544722697606600550145889484236921193237836813 103
UVM_INFO @ 18976282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 92950237691336061956388941219343360537134025243062949611460911141417171322738 103
UVM_INFO @ 7406149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 10346991025786714678252978953772665047812166858332345513145554943028317733564 103
UVM_INFO @ 12489381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 52416254253465508038786989382833782245526299754224254018030751014512170797293 303
UVM_INFO @ 4975716311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 98898336912706009018370822777441357165858936909685923769589585422650851067952 138
UVM_INFO @ 190215203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 8675841617441173591664553124935361612332685060250993316488584376375500970527 214
UVM_INFO @ 964172473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---