Simulation Results: edn/edn1

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.58 %
  • code
  • 95.60 %
  • assert
  • 98.70 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.46 %
  • toggle
  • 96.15 %
  • FSM
  • 94.32 %
Validation stages
V1
100.00%
V2
98.85%
V2S
100.00%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.340s 20.944us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.100s 86.264us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.160s 16.319us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.620s 932.658us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.510s 86.845us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.480s 48.215us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.160s 16.319us 5 5 100.00
edn_csr_aliasing 1.510s 86.845us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.870s 265.930us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.870s 265.930us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.870s 265.930us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.330s 23.433us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.700s 40.756us 200 200 100.00
errs 100 100 100.00
edn_err 1.650s 25.119us 100 100 100.00
disable 93 100 93.00
edn_disable 1.230s 19.585us 50 50 100.00
edn_disable_auto_req_mode 10.020s 500.000us 43 50 86.00
stress_all 30 30 100.00
edn_stress_all 7.060s 1213.695us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.210s 48.811us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.300s 21.451us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.100s 543.800us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.100s 543.800us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.100s 86.264us 1 1 100.00
edn_csr_rw 1.160s 16.319us 5 5 100.00
edn_csr_aliasing 1.510s 86.845us 1 1 100.00
edn_same_csr_outstanding 1.880s 413.242us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.100s 86.264us 1 1 100.00
edn_csr_rw 1.160s 16.319us 5 5 100.00
edn_csr_aliasing 1.510s 86.845us 1 1 100.00
edn_same_csr_outstanding 1.880s 413.242us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 5.320s 372.499us 5 5 100.00
edn_tl_intg_err 3.050s 201.213us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.320s 19.118us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.700s 40.756us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.320s 372.499us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.320s 372.499us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.320s 372.499us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.320s 372.499us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.700s 40.756us 200 200 100.00
edn_sec_cm 5.320s 372.499us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.700s 40.756us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.050s 201.213us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 128.780s 10707.223us 25 30 83.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 86903622405509203029085174317866237515776476010698669882312520320641927764109 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 106905471338465628380601572427631644057224088634147767622149033085816134833190 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 20486095106979083067391358033778717069761919549574687119253428907351289211713 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 29331867326250407811476162596473854793563825467193885536641643177151420052129 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
edn_stress_all_with_rand_reset 51173954637384864638445680176775933796303682938913946993382534872825006402462 350
UVM_INFO @ 3331728405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 24144263347247742663974855736518269281534898208294719500518872385724260081185 147
UVM_INFO @ 457370219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 86437419082627656644215579833784960989542065158511716710252862978841504364849 175
UVM_INFO @ 1274108552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 90120139473117325625246697520243454709723724293294206108948663608176246957117 259
UVM_INFO @ 2470038770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:425) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 62228682589553255084403285633454498696498274507474674127767147897390189337202 94
UVM_INFO @ 13243246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 31167077087412082656653033635347992414046267829141487419427418567775104963870 94
UVM_INFO @ 41726278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 111879281549032635031253554678136082029330468468998530715316566221865863530397 94
UVM_INFO @ 76118697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 71629991213086883743136726973121219489083883615039583276342588594489815264383 241
UVM_INFO @ 23838956591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---