Simulation Results: hmac

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.51 %
  • code
  • 83.35 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 16.000s 417.178us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 19.688us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 22.000s 32.671us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.000s 312.983us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 7.000s 300.115us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 894.000s 281751.624us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 22.000s 32.671us 5 5 100.00
hmac_csr_aliasing 7.000s 300.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 90.000s 7525.025us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 138.000s 12819.247us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 366.000s 37149.223us 30 30 100.00
hmac_test_sha384_vectors 700.000s 20342.689us 75 75 100.00
hmac_test_sha512_vectors 684.000s 215209.543us 75 75 100.00
hmac_test_hmac256_vectors 20.000s 410.128us 50 50 100.00
hmac_test_hmac384_vectors 27.000s 812.378us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 2203.799us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 59.000s 8182.641us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 332.000s 8238.985us 10 10 100.00
error 10 10 100.00
hmac_error 119.000s 42135.831us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 190.000s 13959.390us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 16.000s 417.178us 10 10 100.00
hmac_long_msg 90.000s 7525.025us 10 10 100.00
hmac_back_pressure 138.000s 12819.247us 25 25 100.00
hmac_datapath_stress 332.000s 8238.985us 10 10 100.00
hmac_burst_wr 59.000s 8182.641us 50 50 100.00
hmac_stress_all 1869.000s 140293.769us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 16.000s 417.178us 10 10 100.00
hmac_long_msg 90.000s 7525.025us 10 10 100.00
hmac_back_pressure 138.000s 12819.247us 25 25 100.00
hmac_datapath_stress 332.000s 8238.985us 10 10 100.00
hmac_wipe_secret 190.000s 13959.390us 10 10 100.00
hmac_test_sha256_vectors 366.000s 37149.223us 30 30 100.00
hmac_test_sha384_vectors 700.000s 20342.689us 75 75 100.00
hmac_test_sha512_vectors 684.000s 215209.543us 75 75 100.00
hmac_test_hmac256_vectors 20.000s 410.128us 50 50 100.00
hmac_test_hmac384_vectors 27.000s 812.378us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 2203.799us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 16.000s 417.178us 10 10 100.00
hmac_long_msg 90.000s 7525.025us 10 10 100.00
hmac_back_pressure 138.000s 12819.247us 25 25 100.00
hmac_datapath_stress 332.000s 8238.985us 10 10 100.00
hmac_burst_wr 59.000s 8182.641us 50 50 100.00
hmac_error 119.000s 42135.831us 10 10 100.00
hmac_wipe_secret 190.000s 13959.390us 10 10 100.00
hmac_test_sha256_vectors 366.000s 37149.223us 30 30 100.00
hmac_test_sha384_vectors 700.000s 20342.689us 75 75 100.00
hmac_test_sha512_vectors 684.000s 215209.543us 75 75 100.00
hmac_test_hmac256_vectors 20.000s 410.128us 50 50 100.00
hmac_test_hmac384_vectors 27.000s 812.378us 60 60 100.00
hmac_test_hmac512_vectors 25.000s 2203.799us 75 75 100.00
hmac_stress_all 1869.000s 140293.769us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1869.000s 140293.769us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 3.000s 28.087us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 8.000s 31.116us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 6.000s 841.251us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 6.000s 841.251us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.000s 19.688us 1 1 100.00
hmac_csr_rw 22.000s 32.671us 5 5 100.00
hmac_csr_aliasing 7.000s 300.115us 1 1 100.00
hmac_same_csr_outstanding 3.000s 388.847us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.000s 19.688us 1 1 100.00
hmac_csr_rw 22.000s 32.671us 5 5 100.00
hmac_csr_aliasing 7.000s 300.115us 1 1 100.00
hmac_same_csr_outstanding 3.000s 388.847us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 457.910us 5 5 100.00
hmac_tl_intg_err 5.000s 273.726us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.000s 273.726us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 16.000s 417.178us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.000s 601.105us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 475.000s 46802.630us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 10.873us 1 1 100.00