Simulation Results: keymgr_dpe/darjeeling

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 65.86 %
  • code
  • 82.50 %
  • assert
  • 97.19 %
  • func
  • 17.88 %
  • block
  • 97.98 %
  • line
  • 98.66 %
  • branch
  • 93.43 %
  • toggle
  • 56.39 %
  • FSM
  • 81.54 %
Validation stages
V1
95.65%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 9 10 90.00
keymgr_dpe_smoke 18.000s 2546.091us 9 10 90.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 2.000s 103.009us 1 1 100.00
csr_rw 5 5 100.00
keymgr_dpe_csr_rw 2.000s 40.368us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 5.000s 1231.837us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 3.000s 42.610us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.000s 103.082us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_dpe_csr_rw 2.000s 40.368us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 42.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 10 10 100.00
keymgr_dpe_intr_test 2.000s 13.301us 10 10 100.00
alert_test 10 10 100.00
keymgr_dpe_alert_test 2.000s 18.271us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_dpe_tl_errors 4.000s 639.886us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_dpe_tl_errors 4.000s 639.886us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 103.009us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 40.368us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 42.610us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 88.284us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 103.009us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 40.368us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 42.610us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 88.284us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
keymgr_dpe_sec_cm 11.000s 930.257us 5 5 100.00
keymgr_dpe_tl_intg_err 5.000s 264.156us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 259.594us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 259.594us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 259.594us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 259.594us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 7.000s 344.305us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 11.000s 930.257us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 11.000s 930.257us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert recov_operation_err. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
keymgr_dpe_smoke 17142091763752159230996529217257642991265167703322116709205859253333258510346 106
UVM_INFO @ 19119599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---