Simulation Results: otbn

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.78 %
  • code
  • 87.00 %
  • assert
  • 97.35 %
  • func
  • 100.00 %
  • block
  • 99.33 %
  • line
  • 99.53 %
  • branch
  • 95.19 %
  • toggle
  • 85.66 %
  • FSM
  • 67.61 %
Validation stages
V1
100.00%
V2
99.39%
V2S
98.18%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 12.000s 152.908us 1 1 100.00
otbn_smoke_vectorized 8.000s 38.505us 1 1 100.00
single_binary 100 100 100.00
otbn_single 112.000s 4029.959us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 29.254us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 5.000s 31.507us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 91.408us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 16.036us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 73.235us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 5.000s 31.507us 5 5 100.00
otbn_csr_aliasing 5.000s 16.036us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 42.000s 1525.481us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 29.000s 334.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 60.000s 219.248us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 61.000s 390.949us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 126.000s 2141.958us 9 10 90.00
stress_all 10 10 100.00
otbn_stress_all 103.000s 300.320us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 20.000s 85.359us 60 60 100.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 10.000s 24.302us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 25.000s 284.472us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 13.000s 26.256us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 6.000s 21.551us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 9.000s 248.406us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 9.000s 248.406us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 5.000s 29.254us 1 1 100.00
otbn_csr_rw 5.000s 31.507us 5 5 100.00
otbn_csr_aliasing 5.000s 16.036us 1 1 100.00
otbn_same_csr_outstanding 7.000s 30.990us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 5.000s 29.254us 1 1 100.00
otbn_csr_rw 5.000s 31.507us 5 5 100.00
otbn_csr_aliasing 5.000s 16.036us 1 1 100.00
otbn_same_csr_outstanding 7.000s 30.990us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 11.000s 17.319us 10 10 100.00
otbn_dmem_err 14.000s 39.127us 15 15 100.00
internal_integrity 16 17 94.12
otbn_alu_bignum_mod_err 21.000s 226.710us 5 5 100.00
otbn_controller_ispr_rdata_err 11.000s 60.214us 5 5 100.00
otbn_mac_bignum_acc_err 11.000s 110.101us 5 5 100.00
otbn_urnd_err 8.000s 36.298us 1 2 50.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 8.000s 31.779us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 8.000s 63.663us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 9.000s 340.037us 10 10 100.00
tl_intg_err 30 30 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
otbn_tl_intg_err 43.000s 216.756us 25 25 100.00
passthru_mem_tl_intg_err 5 5 100.00
otbn_passthru_mem_tl_intg_err 63.000s 662.192us 5 5 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 152.908us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 14.000s 39.127us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 11.000s 17.319us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 43.000s 216.756us 25 25 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 20.000s 85.359us 60 60 100.00
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 11.000s 17.319us 10 10 100.00
otbn_dmem_err 14.000s 39.127us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 24.302us 5 5 100.00
otbn_illegal_mem_acc 8.000s 31.779us 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 112.000s 4029.959us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 11.000s 17.319us 10 10 100.00
otbn_dmem_err 14.000s 39.127us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 24.302us 5 5 100.00
otbn_illegal_mem_acc 8.000s 31.779us 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 20.000s 85.359us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 11.000s 17.319us 10 10 100.00
otbn_dmem_err 14.000s 39.127us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 24.302us 5 5 100.00
otbn_illegal_mem_acc 8.000s 31.779us 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 112.000s 4029.959us 100 100 100.00
sec_cm_ctrl_redun 11 12 91.67
otbn_ctrl_redun 18.000s 60.644us 11 12 91.67
sec_cm_pc_ctrl_flow_redun 4 5 80.00
otbn_pc_ctrl_flow_redun 9.000s 31.390us 4 5 80.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 77.000s 194.129us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 77.000s 194.129us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 14.000s 76.441us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 16.000s 81.876us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 434.000s 1506.260us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 434.000s 1506.260us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 10.000s 45.274us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 112.000s 4029.959us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 112.000s 4029.959us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 112.000s 4029.959us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 126.000s 2141.958us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 112.000s 4029.959us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 112.000s 4029.959us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 11.000s 21.662us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 112.000s 4029.959us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 449.000s 6589.616us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
otbn_stress_all_with_rand_reset 438.000s 2251.250us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
otbn_stress_all_with_rand_reset 4004153408543529347145606532211272611094027729876913996646267525521683959519 451
UVM_INFO @ 1370216535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 89880126218077843055719912637403346569462756747008794484601858020428843395267 183
UVM_INFO @ 4288526739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 33209975692369532350334947414558372622466288588081006881602526256570794295526 253
UVM_INFO @ 1494018647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 35276495002641254433699957344078212141601236820445313259449460910476367626580 256
UVM_INFO @ 2577580585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 81014724519580102290516075088352114753743656178434036285188403668543185207334 206
UVM_INFO @ 831217074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 9213785835221380397541076245291381804998207599801067686109382096718108621121 195
UVM_INFO @ 610310224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 54033951927292941610769180182333436582886542567907494768749412002828794530253 227
UVM_INFO @ 2228252942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_rf_bignum_intg_err 65163154372596295066802302897779473105763500902003552228620012541526763149282 112
UVM_INFO @ 132661918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_pc_ctrl_flow_redun 95458656983615394061522083351446541179385981271745296448093447960672976832356 107
UVM_INFO @ 119017456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_stack_addr_integ_chk 16015577403088525330081373320220592016101607541790420533300572702175179394778 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,158): (time 18289184 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 18289184 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 18289184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_ctrl_redun 8916367307839998726215009725126264636887557155072618531925066361039036307150 118
UVM_ERROR @ 52252510 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 52252510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi 51180022412719033901199705038716683734589653961884577124073533028206191525570 168
UVM_INFO @ 1066302426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 41157117623067462431072220745637811923938304523047792931105191957989728823945 109
UVM_ERROR @ 36297857 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 36297857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---