Simulation Results: otp_ctrl

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.31 %
  • code
  • 81.13 %
  • assert
  • 94.94 %
  • func
  • 82.85 %
  • line
  • 88.53 %
  • branch
  • 86.74 %
  • cond
  • 88.60 %
  • toggle
  • 88.65 %
  • FSM
  • 53.12 %
Validation stages
V1
84.62%
V2
70.25%
V2S
71.36%
V3
14.85%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 3.090s 864.889us 1 1 100.00
smoke 7 10 70.00
otp_ctrl_smoke 19.040s 4891.220us 7 10 70.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.820s 316.082us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.500s 58.163us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 12.850s 5114.138us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.290s 89.083us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.680s 258.697us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.500s 58.163us 5 5 100.00
otp_ctrl_csr_aliasing 5.290s 89.083us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.270s 161.020us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.220s 82.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 146.110s 7597.279us 0 1 0.00
init_fail 199 300 66.33
otp_ctrl_init_fail 8.220s 2955.147us 199 300 66.33
partition_check 24 60 40.00
otp_ctrl_background_chks 22.810s 16344.747us 5 10 50.00
otp_ctrl_check_fail 44.320s 22090.607us 19 50 38.00
regwen_during_otp_init 18 30 60.00
otp_ctrl_regwen 13.840s 1368.697us 18 30 60.00
partition_lock 13 30 43.33
otp_ctrl_dai_lock 33.050s 2130.410us 13 30 43.33
interface_key_check 4 10 40.00
otp_ctrl_parallel_key_req 23.300s 1336.428us 4 10 40.00
lc_interactions 186 210 88.57
otp_ctrl_parallel_lc_req 19.820s 2895.874us 6 10 60.00
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
otp_dai_errors 20 25 80.00
otp_ctrl_dai_errs 70.450s 10008.871us 20 25 80.00
otp_macro_errors 5 10 50.00
otp_ctrl_macro_errs 57.350s 9487.159us 5 10 50.00
test_access 2 10 20.00
otp_ctrl_test_access 23.850s 14512.572us 2 10 20.00
stress_all 1 10 10.00
otp_ctrl_stress_all 212.630s 73362.412us 1 10 10.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.660s 166.026us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 4.510s 1136.163us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 10.460s 3491.091us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 10.460s 3491.091us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 3.820s 316.082us 1 1 100.00
otp_ctrl_csr_rw 2.500s 58.163us 5 5 100.00
otp_ctrl_csr_aliasing 5.290s 89.083us 1 1 100.00
otp_ctrl_same_csr_outstanding 5.360s 607.829us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 3.820s 316.082us 1 1 100.00
otp_ctrl_csr_rw 2.500s 58.163us 5 5 100.00
otp_ctrl_csr_aliasing 5.290s 89.083us 1 1 100.00
otp_ctrl_same_csr_outstanding 5.360s 607.829us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
otp_ctrl_tl_intg_err 38.630s 5994.212us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 38.630s 5994.212us 25 25 100.00
sec_cm_secret_mem_scramble 7 10 70.00
otp_ctrl_smoke 19.040s 4891.220us 7 10 70.00
sec_cm_part_mem_digest 7 10 70.00
otp_ctrl_smoke 19.040s 4891.220us 7 10 70.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_dai_fsm_local_esc 185 205 90.24
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_lci_fsm_local_esc 180 200 90.00
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
sec_cm_kdi_fsm_local_esc 180 200 90.00
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
sec_cm_part_fsm_local_esc 185 210 88.10
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
otp_ctrl_macro_errs 57.350s 9487.159us 5 10 50.00
sec_cm_scrmbl_fsm_local_esc 180 200 90.00
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
sec_cm_timer_fsm_local_esc 185 205 90.24
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_dai_fsm_global_esc 185 205 90.24
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_lci_fsm_global_esc 180 200 90.00
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
sec_cm_kdi_fsm_global_esc 180 200 90.00
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
sec_cm_part_fsm_global_esc 185 210 88.10
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
otp_ctrl_macro_errs 57.350s 9487.159us 5 10 50.00
sec_cm_scrmbl_fsm_global_esc 180 200 90.00
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
sec_cm_timer_fsm_global_esc 185 205 90.24
otp_ctrl_parallel_lc_esc 79.400s 31597.955us 180 200 90.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_part_data_reg_integrity 199 300 66.33
otp_ctrl_init_fail 8.220s 2955.147us 199 300 66.33
sec_cm_part_data_reg_bkgn_chk 19 50 38.00
otp_ctrl_check_fail 44.320s 22090.607us 19 50 38.00
sec_cm_part_mem_regren 13 30 43.33
otp_ctrl_dai_lock 33.050s 2130.410us 13 30 43.33
sec_cm_part_mem_sw_unreadable 13 30 43.33
otp_ctrl_dai_lock 33.050s 2130.410us 13 30 43.33
sec_cm_part_mem_sw_unwritable 13 30 43.33
otp_ctrl_dai_lock 33.050s 2130.410us 13 30 43.33
sec_cm_lc_part_mem_sw_noaccess 13 30 43.33
otp_ctrl_dai_lock 33.050s 2130.410us 13 30 43.33
sec_cm_access_ctrl_mubi 13 30 43.33
otp_ctrl_dai_lock 33.050s 2130.410us 13 30 43.33
sec_cm_token_valid_ctrl_mubi 7 10 70.00
otp_ctrl_smoke 19.040s 4891.220us 7 10 70.00
sec_cm_lc_ctrl_intersig_mubi 13 30 43.33
otp_ctrl_dai_lock 33.050s 2130.410us 13 30 43.33
sec_cm_test_bus_lc_gated 7 10 70.00
otp_ctrl_smoke 19.040s 4891.220us 7 10 70.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 502.900s 73171.504us 5 5 100.00
sec_cm_direct_access_config_regwen 18 30 60.00
otp_ctrl_regwen 13.840s 1368.697us 18 30 60.00
sec_cm_check_trigger_config_regwen 7 10 70.00
otp_ctrl_smoke 19.040s 4891.220us 7 10 70.00
sec_cm_check_config_regwen 7 10 70.00
otp_ctrl_smoke 19.040s 4891.220us 7 10 70.00
sec_cm_macro_mem_integrity 5 10 50.00
otp_ctrl_macro_errs 57.350s 9487.159us 5 10 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 73.620s 26642.503us 0 1 0.00
stress_all_with_rand_reset 15 100 15.00
otp_ctrl_stress_all_with_rand_reset 3600.138s 0.000us 15 100 15.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 114 test runs
otp_ctrl_smoke 59078240821702321845461309759209241094492003751400337555144720478119778413866 2800
UVM_INFO @ 362405683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_smoke 102454454663256182860231635798021016513526125329941705170445963180886815813900 7206
UVM_INFO @ 281785691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 67700075529551844347889182936700889595838159735185697552943601346887842633629 4637
UVM_INFO @ 710483475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_smoke 36089812719746523242006942164516510421745684764847433951028636885423649482627 6558
UVM_INFO @ 3848385824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 43705949625504149491739229106781943782997409295736667630051337987593408001433 1766
UVM_INFO @ 124485413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 100355913662232164122629593182521227294461188046442090890451193723743468363063 1942
UVM_INFO @ 82662189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 16016702570853892391298895326576373606657726966703951052042555188177672413184 588
UVM_INFO @ 59715018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 50717883681792367934404777656059918271136000954678189424972651486255676906726 1906
UVM_INFO @ 137736434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 22006822517456961008417668620596059443698514122982634128751654077415786666827 1249
UVM_INFO @ 63119547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 80731162954158686389210058808122286442900575286617319857824899352335580525825 751
UVM_INFO @ 131961729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 15993986089505511182471275068271956890936360773537148591757787952281397578735 7448
UVM_INFO @ 560105877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 40410345690801951456632247511356609184985668117415559607609576799974840064855 1091
UVM_INFO @ 67471474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 99973021701092742595119308765831210426081319551676811287563611546758627362641 2646
UVM_INFO @ 137290712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 9483330113910399633582705414491890881577317432635262196691356828498800929986 1689
UVM_INFO @ 115469208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 26746604328792363579179490017324653386340793435333985628107949960679687199173 2826
UVM_INFO @ 252592802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 113785290922906490406332926010456844256303374008823523001400446573069084335856 3442
UVM_INFO @ 215125617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 24578809796051379467920306679512206461484515716040936333481783788988071761333 2222
UVM_INFO @ 160628416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 77736732790982262686317747847726864583974578101674644148773721440344247620626 352
UVM_INFO @ 77469391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 44391804931760303738920614703063745609610827269207558936457800858656096228089 775
UVM_INFO @ 879208548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 84139282309412476248459982916938868783284769248040265059663498090754885300826 9752
UVM_INFO @ 252934298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 55023738374384150526384380752277068901507555545496504016868576172220357940669 315
UVM_INFO @ 50190388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 50890613904182017855933174554482767680206171897661365337593738258985138586742 681
UVM_INFO @ 82014058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 95856879084812553271559474833211204450459674894535920300413435175814430362354 583
UVM_INFO @ 52212396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 36621418678710618234314894625160967234385022525394388260060768180196544989902 1099
UVM_INFO @ 52313863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 4137741185998751664911604310058362872807346473643422797451704396111862106806 287
UVM_INFO @ 150781891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 67397350011718900618862128384187582781684797418530615036864066858777243272285 579
UVM_INFO @ 925328681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 21950037520509854223089856748871748316903890168480000749584197803233592807107 271
UVM_INFO @ 85865441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 65480209392951814177982031044382618028713863210284686111556314020492056312866 105
UVM_INFO @ 183143352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 46894961112076636383966844668975609072902754657353884070200673307548209180775 1683
UVM_INFO @ 297711402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 15840792060345907367918144281747327371717573717229966802164515234443297079929 231
UVM_INFO @ 47069545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 70554481467397786876962955393773476484620307452687262459796637609939164282359 1541
UVM_INFO @ 54387551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 34813080646460823533646330127491894185908427923160764551645563659863124400240 105
UVM_INFO @ 60064004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 100647633486527622475972288121133556566937318292777723596921138994141876345167 147
UVM_INFO @ 756365727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 79075472534754442460375045502140014108550346935531299517062974583205404759817 147
UVM_INFO @ 201937943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 83129959239845140777050778001162253245942898410390439882010117822906949855743 105
UVM_INFO @ 134069866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 41454601010744729940840408331562619192572459558890543723740739075115690619947 331
UVM_INFO @ 42796086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 84865463532392198011794737721602649353880354786500972232532867183555423199942 329
UVM_INFO @ 79511790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 26787960724448122057754108355961664139940597274011950093466323872097781266998 457
UVM_INFO @ 612605524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 51384706022429302387840935727083734302383659904796016186981422726108923382162 1651
UVM_INFO @ 62328076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 24208374285186153609710447469225879654588669308030704168970377482895714206710 105
UVM_INFO @ 139264158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 15833817940929283979702742148735470903141954506503751255044286616278094564503 2189
UVM_INFO @ 1307673702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 33945781356023880629695064934756584526621891809051476113433293270253372629675 1317
UVM_INFO @ 52870636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 70579018351680474819306833688607944844801140166693769207879851696354889843552 497
UVM_INFO @ 43344917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 74326989309775569135118554707802132894062086814798177097340904073979958292969 1181
UVM_INFO @ 54349249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 115330853729680775371202993889962841909143170324521507940207924637031490304357 1219
UVM_INFO @ 153947029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 97900404992584669184158978700224792856995779405458935579039403697075604722990 399
UVM_INFO @ 90947462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 50264586901241310836268806288241425616579081483058175012561792098547413660308 1227
UVM_INFO @ 107062736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 77763829935007808481234939047841568960803129318252791597312672349549624364603 763
UVM_INFO @ 129906561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 38412270315288816058875057888015266127876776840557723668410951669055816096736 231
UVM_INFO @ 552675425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 70943733083536819560634037583081450191668163746443808021026869651402587627211 415
UVM_INFO @ 149727041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 40355513483724236854429158212214903960740971247663116613534727302928904297667 189
UVM_INFO @ 56571718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 21476080533567908243138715435875311384346276779757163397205087205699018205232 1061
UVM_INFO @ 76419331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 31771663334655164008907610033962278057335289318855242484484864137714485068324 231
UVM_INFO @ 667405637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 6967712987479060609434423892151702854150695920917476850231021164713673223307 605
UVM_INFO @ 285966880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 23971672532894808202650506366591708269114305968063784698223077722750037993399 1593
UVM_INFO @ 922793668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 87980148822722753269214893282287945084615065465494121033198427853148245057951 665
UVM_INFO @ 775195289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 88881533340875133573764749699064579533056465989739021680875977444713514508004 499
UVM_INFO @ 37112725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 20199497210641970081583564740816324939947563229037730815243388102740725089423 1061
UVM_INFO @ 69873432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 68344593475760760582691649007791703226292182546298738768099521451674940215121 557
UVM_INFO @ 60908922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 80086773702173588483607139349832482428731979058257306950868968057826319925304 247
UVM_INFO @ 126754369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 2478623535661257688604435404048744197883162198687318750553902642160493313341 1423
UVM_INFO @ 56011777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 104407585352825937475926179943085732585236006818951218689554120277898082786751 607
UVM_INFO @ 51981608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 4502544001516388804624470753037618382009084556556495644726796998330519360557 2245
UVM_INFO @ 1081698874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 55990169334794133244386622577016826927164257360858936315588150585989189600091 347
UVM_INFO @ 41561175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 89615706580884811900956840542960344768827373346045909266940146053787962000532 189
UVM_INFO @ 98106335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 53271251756662395466006559443433490170312709914196126598810948169037402599423 105
UVM_INFO @ 512367665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 107080613968505052542050385957597776954554420916536281043307340320599452288561 607
UVM_INFO @ 55232383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 31364922510393240706594762569222257723301769101089950689949802104192872514269 415
UVM_INFO @ 56033152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 112283713370338378906438776387481137857919020523906727449835134342497389457414 331
UVM_INFO @ 65431402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 64494637662719084851877996921267543538143173718062463777266189417323424816090 413
UVM_INFO @ 56116163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 11216740742448836861936481987792818624201139458110569315854210999291268605099 105
UVM_INFO @ 123981141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 4626514958901514805492267422286330836816078875426373217211307294333548369087 609
UVM_INFO @ 45599466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 11617151784091644992678006009806473138434637710917761423095281826381691517554 2417
UVM_INFO @ 150616600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 77462814801717399714015818322836573260147214865433337483302996595008664998662 1517
UVM_INFO @ 225796080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 75681076746988822526111504773156462599963806081899539333291280783606851175847 2121
UVM_INFO @ 1413114843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 58338695789471748187050841138463995785708276732210107580208937902923137423087 797
UVM_INFO @ 85389210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 101021578433809839583243457436058374744690191356930655284610555150097593865545 609
UVM_INFO @ 40596311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 72843555083072233800327051455387791483788224037937256560955604199744619500666 1073
UVM_INFO @ 54928915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 79472949739941933533061412176570109840086805697647850222751365553989606799069 1269
UVM_INFO @ 80304029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 35200679159526610511925363748868297236100064269197758009400647006975017481948 623
UVM_INFO @ 39541560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 87030801216190880687397857525693443789105841417654726529909290305744769511263 189
UVM_INFO @ 33464204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 44216384747722007414176760558157318232994354880821973633258658814953387978564 667
UVM_INFO @ 85067852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 3925888531054475018565414133820440031237620179546592530010879873021324388957 1155
UVM_INFO @ 232953585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 94627109471298849456109013199862085758252026165353099291471427123647539612907 723
UVM_INFO @ 896218305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 81457688759041624558401318466501583756339855485636611963703755668588600363165 807
UVM_INFO @ 1181932777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 95451295272879178146290839370696929334786069130629870365561977409108188356546 1767
UVM_INFO @ 58695431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 81946924808804903365453211441931834287432749465085789348109404595559121385639 457
UVM_INFO @ 75372366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 106417376558213310591670129698300720578075439025255043000793009384688639569439 905
UVM_INFO @ 185650889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 45606834428238119201002893708133018657604727561910295195199610538762847855009 733
UVM_INFO @ 130858761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 38492109384704166841757808506756284688934962144993482203297466670593242999060 2853
UVM_INFO @ 1239599092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 35703185417854329679110153679441123662364369487236546927791796110519393086539 829
UVM_INFO @ 59532939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 67120332925489514858410570173884409408421824058936205367953790972732774144076 1355
UVM_INFO @ 104673572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 49452174023582943106608254979942170451663859386541132860622682043254820541919 105
UVM_INFO @ 47871266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 71507638235916080776525680506426723128368695663105459145716612439483201895738 331
UVM_INFO @ 36778400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 22297330910763725748567860424302361989571426005092477692004232741557124863650 2837
UVM_INFO @ 1227237610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 106029760709654120557626352380146436574465922342679422541746132429700988216248 599
UVM_INFO @ 81252177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 103642343308993881375682030425918086124729714698811730084378567053830389326089 291
UVM_INFO @ 70757310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 26959660554071320940693233989363269428166918043465075033501307946897191108773 247
UVM_INFO @ 42902817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 51083971945443538321582906158455441573137445778973886220352842452804982803059 623
UVM_INFO @ 163049596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 95518488381487854482320541951555062719918834297274916447166088878431391831722 1151
UVM_INFO @ 191005093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 60557476774375301289457185026004392115625167071381517146176925519788798289638 315
UVM_INFO @ 66383034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 38194664399938297647295454586013145635976756777829205898927732792388195415027 515
UVM_INFO @ 135172794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 67730930692655026058406229832814398764905121750962893815785959962182450565829 1821
UVM_INFO @ 105379010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 106069870029959489905854796123386159048258575758988815787685981860611348795992 189
UVM_INFO @ 119308808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 28418040084265317589452427813440187967983845467562587951747898579848066802045 205
UVM_INFO @ 220249377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 100204221114619630447603344134270822853731580409038344982593284264598731723330 1723
UVM_INFO @ 67001065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 8170407473629772866301130240629380956541002149299789318507545733168198778355 663
UVM_INFO @ 71250554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 38160687555031891452778348875827449855041023695543245793818543792678106757905 575
UVM_INFO @ 88188801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 92303163410195865813472576940735922017884463389763234622965853799025935863132 231
UVM_INFO @ 93792929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 58779500069410814650361953097571335864917244155950245434759544720103006700175 583
UVM_INFO @ 705413153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 13733096035099961276308741403756137221686695475230610338171139601632972612878 2017
UVM_INFO @ 1041265205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 99627204548904928315610217183633264284419340004985145964069545849978802969913 145
UVM_INFO @ 61883531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 59382318899106367526173085779823489177883711908574781278168472831456436006062 679
UVM_INFO @ 108524289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_init_fail 92034462150939837495288144073068348408799446609860692420571727081412939891233 639
UVM_INFO @ 43584959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 80 test runs
otp_ctrl_dai_lock 23931788430372648803118579432535974639942955691095743400351739845893928322466 1864
UVM_INFO @ 156688355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 91182622806424262023634036881397491920238971223038472792800558349812701705460 3079
UVM_INFO @ 2378744540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68844326700125226869535014886869365037377742526389381441407375697081510011685 2552
UVM_INFO @ 9619623503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 31780406237136731336315619955896363434159129372212522579777659752971145039489 870
UVM_INFO @ 94163554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 99578002171869501011356439671757920686004482217928862740592560051434211214458 3204
UVM_INFO @ 910227962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 7155645212091372330247048132953031617933227438183942395801532033196849729914 6185
UVM_INFO @ 1257083556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 63573322628744697450563522098876909542450008394444689571056461740510865293305 6953
UVM_INFO @ 269697487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 113035941178514780300388514883759525693302165491665785908302901911365311085317 218
UVM_INFO @ 919864060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 98290498502858848469456843029933786335308996818113840056373818287261346499637 6058
UVM_INFO @ 8203623263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 26080869884607571866279417607075340245940629355554613494359065482765726811960 1096
UVM_INFO @ 94349102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 1291454934594330735076561849707993634223204582933679245977867334215927322686 3578
UVM_INFO @ 254847961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 9393218982232281283060174157079401849469234621082151178678821467607381661523 13112
UVM_INFO @ 641302044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 85473122649828502804524813331510111167086739166093774126228953869394674034629 1098
UVM_INFO @ 109754357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 90510172150680850814113333002582526443019021751117787400253751191671870919187 9741
UVM_INFO @ 493092030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 63370604500408087481010219843829073669846334440384110582251939584378163472954 488
UVM_INFO @ 276270958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 82433439307738432610741884776882004431707671000136353884819978414470871972785 1072
UVM_INFO @ 657917776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 8723929304171251007727455382780403202199647984168159223966750394042084998893 4160
UVM_INFO @ 287682539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 16638806625579142044816654690573238645084835659896617381706958814622608210239 9860
UVM_INFO @ 1187522194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 48819212403297319630158743204869578672968806542908504393109324939704854335984 2510
UVM_INFO @ 190874688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 31507230405465901150279176836500314564149061386895330932308367208496776494952 3300
UVM_INFO @ 254246069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 47197070616596897438994028491288730336574892834475298235956708782111023188290 9579
UVM_INFO @ 2697050308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 47997768729169778078597140302786314257925930345787996337920685090456697803565 4896
UVM_INFO @ 461290943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_background_chks 85142603907402067881463200888556835151308528447790677691129716607054387610575 1944
UVM_INFO @ 686949555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_req 59735359495595190678574031211546326808358363153105857867436653013920295499259 2220
UVM_INFO @ 292090592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 84312665549109852677630846450345669388304938653602763915049292368853535616976 4741
UVM_INFO @ 340604491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 91840805410184391539211258228096200665178821199665093681907054698780693906611 1954
UVM_INFO @ 3192098406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 74536473447368267245989728060641948052935591964839646749722993800838250342728 1711
UVM_INFO @ 1287544236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90735111730992232889390559963217995432385296007445033743013305882946162122099 184
UVM_INFO @ 293873097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64732255482823801686215021126264981145342375860452280536900648744334445220764 11466
UVM_INFO @ 1311312270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 105819158614901187241180113853644175547275380615742813675501365087743124015729 2612
UVM_INFO @ 237807195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 21135578577601263724316896918559926120002317235304687090368059559934392197129 8926
UVM_INFO @ 181527636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 82129365504709883683368572086161178361151146864215436882457834098474484907758 16587
UVM_INFO @ 2669483657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 12034948044380843985988255154226176413350350155635711010987479030327248298781 1746
UVM_INFO @ 2302326753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59504494584482641123282581804980038216574434901937713235772130305571095452742 9154
UVM_INFO @ 414333803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 107611116200551067691414122322313243786220367342776470321554699927667189383594 688
UVM_INFO @ 405274695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 60355110464174276329269676739704195495720486269021762969023194005678507946771 9404
UVM_INFO @ 184329335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 105917952643541127119280426461374271279224871253581254775363760043790229335386 1038
UVM_INFO @ 186529180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55977617605223661367073688685434147733662734035709329846533362316214944231966 3946
UVM_INFO @ 603160598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 10049343700974360691983942587653721158019761284301093663943225153375297881945 3816
UVM_INFO @ 179943857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 69314248665114994186914254701016763120006783378917057941754398274476378614909 5917
UVM_INFO @ 1710848715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 30658517175044329613183232410707160889628188029388985506936377498658235300632 486
UVM_INFO @ 41266425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 17331462353651693537089362283001024014885617757943441023443170886204765602582 4150
UVM_INFO @ 1290426747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 70020518924886902521109425752389268954439211113195132228971019558540110130107 2472
UVM_INFO @ 407099909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 72047924723866555034174041142407514326326190886537457112661211482195666933490 2170
UVM_INFO @ 438846530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84199446862022198306589197392147241020660462048685653945707542883595562458574 27265
UVM_INFO @ 4972902393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 30124791640174381880427936854557013046878705578431432287199372403651026471785 618
UVM_INFO @ 644393347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33011916598811652678730679971031840059566395304208331802779902126634333228415 5393
UVM_INFO @ 732838463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 108092768097954504589140947112260833686190461868654477992848142306643929780671 168
UVM_INFO @ 47103374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 71102089547651448354396504018887941589607737368278488852951158629665286493523 600
UVM_INFO @ 61372597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4584376151696903806714685911332247503802042214370350268169227510698020462150 5540
UVM_INFO @ 733666598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 87347616838099761693261302968240059311387374011472861704131995433530287668877 4006
UVM_INFO @ 207261238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 101634231179051477028366280808756256719170016824331716487288187171389089705503 166
UVM_INFO @ 77661596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114073952725718327788387078539650562669948594123103888315227843546435989742550 3432
UVM_INFO @ 5506947889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109072934816491509353692167921015212590594956204492263917090833417202957485649 260
UVM_INFO @ 869721330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 40688337824240940441884605073980941479626315689043062731752291727627413362363 3828
UVM_INFO @ 91756672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99515202037054120648046991026495056632354380122517616721824854875527903796250 2792
UVM_INFO @ 1413750662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80306241538728175120142657449968784061121444828734413389834160848828145354822 2452
UVM_INFO @ 1959670363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14917336434165267551978364952789274927531883651140166153396443577118241969041 6949
UVM_INFO @ 1813749510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 81834179224132310128158972993244280135577857646716287125206795056539776759439 1800
UVM_INFO @ 1165206597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 70354236377278899611016642564094464512251090820541796589123636879205635731807 1650
UVM_INFO @ 54504956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41937745302730596702359927305919067463910212190248561866822050138468025050872 17064
UVM_INFO @ 6225469591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68760447963344358653701116475286843597213168616917787573098789896874059173307 1579
UVM_INFO @ 811193065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38118427076175635642213354628727249697831456470193765748674353744102259773500 988
UVM_INFO @ 155726464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 92127065657753695052477993380507509102855091421247684001549974660277522658564 872
UVM_INFO @ 89498759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56525489487336890505160008564280478379947416044816216779223207535930305632167 11620
UVM_INFO @ 7015018790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34971505743437659864063872602644707183280530199890349088659291371953990379484 1914
UVM_INFO @ 11759288218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 114442186273888582464086841309211529965379879799652192887097764837028994206884 356
UVM_INFO @ 108330241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 64942929463639373451821460488505122981723043566333239584724319554812564709798 4859
UVM_INFO @ 3674519419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 44392721237994972910063388293608677076406833613927632025763333802195319639069 2564
UVM_INFO @ 77474573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32299144837210798285917740359567744469735497399526143322516454129478935284772 6702
UVM_INFO @ 668987159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 68792979508990170253769497491685678354511047746951041687518096429544193723254 996
UVM_INFO @ 77967827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 73148419628934753311874579944727163031527366317641073525600396883253984353866 216
UVM_INFO @ 56179554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 55821461930114737951918865504600700595450797256582081308778550473095792067243 168
UVM_INFO @ 525700516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 7652041662988026080016988642415007602263442932527738072598824591865140209478 502
UVM_INFO @ 55975121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 104822909158979209659060384215794928891849015747426712441178977120882615440291 218
UVM_INFO @ 106706310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 93197487960700912145256721171023613017133049149746280517331897468651586180765 2004
UVM_INFO @ 1344363220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 93783688113390445815522329169994889512495320443600487724475678257953477887270 1686
UVM_INFO @ 78437889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 51098394109721151429388165032047083457526616174440541123940821240111309742462 3470
UVM_INFO @ 1639889402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 92206816263051427876899641661101676713791481366736090018134940647596390053424 4056
UVM_INFO @ 1508325711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 69394501125818619776268490619366587914576630509480790725845933502410141365657 1300
UVM_INFO @ 452044228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 33 test runs
otp_ctrl_background_chks 30296018763157808100095878774076165241145432932283741422406430448315940721368 1649
UVM_INFO @ 214151822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 102393742020700356536802805542107551639628553752892411963679860042724443533575 9146
UVM_INFO @ 344497696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94196837740880358705628704965351112001044041226179036631646795172704101967752 1016
UVM_INFO @ 939301529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60823990043626522876745633728117594158458533208424771576591429791284126731080 7242
UVM_INFO @ 1516145464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 90314035019932894440033093753485897340052741128238700471983000271840459682954 1060
UVM_INFO @ 1831203319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 100225226768952298642758559039822025558053194622203191637744006148137779420208 10566
UVM_INFO @ 303188467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 19509419988982825422627752640899399805202850291848976889334734332730517239101 4821
UVM_INFO @ 2057681735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 111184845027892487591994871783894485755456800378101614023898992093786894124206 24800
UVM_INFO @ 1336427824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50973515810690540903332951004412299214394184175489896970779048907799961755054 11212
UVM_INFO @ 2465799527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78252195027931387280357855196470888529821842790580589993804409847396315364705 15852
UVM_INFO @ 1775197437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 44985809857056529532852114244777472113919815506349515080508629924352477920591 14721
UVM_INFO @ 1387212679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96940765516755661424151517805034552248609753982657864059713975077031757067531 182
UVM_INFO @ 122499500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15016471931394788503547362161831322072004999725753916830408705442234692837536 8046
UVM_INFO @ 4984809231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43891408460930326885688748463997386865015494940141686245570461268432664421185 198
UVM_INFO @ 42254671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 23781232774953401478813225127105992090652461637673251394158492599228131164706 366
UVM_INFO @ 63570442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23385918593402906368509116141703204906193951269712042710353730358248386070198 2244
UVM_INFO @ 11267447646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 3735987637471818280707854215180465876029266888606963586257426593702486915261 4243
UVM_INFO @ 436954954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4034980490101991796640020417090851839589811636637502206177372977066300610871 2257
UVM_INFO @ 16524832566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 33691983747295459823315573408863199907920322372264703864830322727149835758905 9683
UVM_INFO @ 3531478113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10113016038443534692483782014615263314379075534658813947157707547463177910308 2415
UVM_INFO @ 841927954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107163480676293386736848803747715174381457154000706310264895552254272295651283 10805
UVM_INFO @ 28110877787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81626913724193154412034152079023969253891093953747274987389252786752532399640 1698
UVM_INFO @ 556976202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62087523083660163264123604607466678189573472874245525268065647895206249470505 432
UVM_INFO @ 138373829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 20438619698959002702311388254103308839520011310734151977084057947455444082553 2990
UVM_INFO @ 8963328255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56691077309118038697891673729117510432306518982121610300083528194013888380211 1267
UVM_INFO @ 628118224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1646812701745517853826261227092432295644211968110469388610237074307630410593 5822
UVM_INFO @ 10014676737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83136075921282599891796974333771226305411632332437255245266963962132177568925 5321
UVM_INFO @ 1010286936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112150182327535784986947951456045883757918559206472136000988333522826837934289 1214
UVM_INFO @ 11509548143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97188271735616603948221104146519795918171687395720839598067007142798667089959 1332
UVM_INFO @ 18892920494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 87134537226531907510305765351196888718588535962849623284119187643001454948178 6007
UVM_INFO @ 5437425932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77563901853417546696460998235348564244626791352127028985320611382165545060947 7411
UVM_INFO @ 1014252618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22731362326980660823656587506776367345487958588929150447175036912826404184653 1784
UVM_INFO @ 703164491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102114028010375970658707775134688217939182229808082065857369581744856552268169 9998
UVM_INFO @ 271194307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 27 test runs
otp_ctrl_check_fail 38508073912446754340414612579997156424538316981801014243875412665345603500228 9481
UVM_INFO @ 754346999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 34993188494164003298359745626660164450805735562200736291568118302658589359053 622
UVM_INFO @ 71071207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 20785045921834032136924737920555136945367041296201949539638242264544454799357 182
UVM_INFO @ 1706344744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 76510092796827802001445990249212897348435445747821698346618788034528309623370 748
UVM_INFO @ 150262746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 52390773877707172620722918328374585267163288955537386395871101184584998008866 3805
UVM_INFO @ 1412472212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35012123507839602888919481217454952091633593985732678685767224260458335455520 4520
UVM_INFO @ 5672240798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 94556985815163576982676515307173364553408607071491854845195346610300027768928 23726
UVM_INFO @ 5387717802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 98237389871684092047924221672977059241798523081219953527435889076131542142559 19912
UVM_INFO @ 3652375084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 51921888888591326830899254573347807136201275687304930553004786715094097504271 7404
UVM_INFO @ 1037079565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 74172967682019586321153242957502982333794696609669237208874004159310620025838 1912
UVM_INFO @ 156628394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 46595126336222005233962148755404591472390084661123337713014011874923491473352 2570
UVM_INFO @ 2422152457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 97391457982137092377160046726304278952455662839431735034210067363154891155529 888
UVM_INFO @ 1729441173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 113193321130752901972928295095535469360482564561389691011682773596957911639129 2008
UVM_INFO @ 70067603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 49277331309961557615434289822090510957266604217434556641575792462158355625682 6774
UVM_INFO @ 2392249878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 31340426055536531229391827941492567571796168321078849356265844678579457423216 3270
UVM_INFO @ 3739611078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 56815651610230100353109590926943034087452734371664123403372112203721614632039 1970
UVM_INFO @ 1339323977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 68354012835925823243550167373162785805090399091984188644804468177671664246481 18208
UVM_INFO @ 22090606661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 24692819005935212074457638519925637450151051968272670052658408080198948852680 2589
UVM_INFO @ 4435157012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 20619049924473665450305971326925084107391687284820519890944493874308778332428 4065
UVM_INFO @ 650080396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 87552174057173967027274238271788958945278029382601410635433533347905860256370 9538
UVM_INFO @ 1200425298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 111955964649684585745735195418926875096645386265335831656888749576943864473970 4905
UVM_INFO @ 1909250296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 41044501166330318352903581936852277276224558247494204820032346053155023844334 4484
UVM_INFO @ 784257363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 92350507669374054209123054886892396992160870560255018183498244946221904996004 8633
UVM_INFO @ 1948743651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 100216498066339845901855866366865931022593285812645394773343502379529631446287 3547
UVM_INFO @ 308166222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103732446566557781148023155763938457471978226648026084833352759453853685992321 6628
UVM_INFO @ 1887643453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51605729920431471413232754486625756508683909658388249826698193820952509477611 51711
UVM_INFO @ 1058595330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75730738032738809353748726694095364043718516257019602832427608852305989428563 350
UVM_INFO @ 471002673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:764) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 13 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 31250434200385253645581039172084342871768840608203980697410974597901428581010 103
UVM_INFO @ 148580990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80617448138582095169925803702365105944664931467682095633145217069808549781067 97
UVM_INFO @ 60101823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106999475763360885120770313960298045813305210474835337452667480569115941063965 97
UVM_INFO @ 33424207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38098313286030303229066968744450299158782546114758734879485911737220373686763 545
UVM_INFO @ 2037068355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73269586261732624722071718472979196699161514810730055969389619128006978787553 6049
UVM_INFO @ 310835777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65450975814082303006146580668684651763918399152848834851077931163048021378086 3258
UVM_INFO @ 2113326476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9667779474344927308224942248698022142246880266299756833912496845262266551644 12522
UVM_INFO @ 892024028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63350895407557626749511462425968092739206343676297546245877253081487075903803 97
UVM_INFO @ 125565739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61959227094131383989911325684838231316244060288899993753269305644434219085699 40154
UVM_INFO @ 1566666814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7564395467146607900781025536831166192070496190747083903335420645826388861273 328
UVM_INFO @ 17857842177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57088183082573331617733890154090132765439100170420298104591597150431432222952 4194
UVM_INFO @ 9935071242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97117956571617688497912104925157696942709314464056300710348470375228837116204 167
UVM_INFO @ 14220302057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76316809608620275799429192261961500910211423147975025411906002026040421521476 19344
UVM_INFO @ 731087241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2202) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 11 test runs
otp_ctrl_stress_all_with_rand_reset 101142241841004924892072924077406687576423226002761823977017222905372225549874 525
UVM_INFO @ 279977612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85687860271274514007492500287111691722048707484337830235358711359963231058290 5123
UVM_INFO @ 12216962326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113191686586063538898738556561296358970148493907782369283577447321026641612412 98
UVM_INFO @ 90644697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52765585844623419168445098378734632187051883879973348628677026385830852429527 2439
UVM_INFO @ 13765204807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42220766192374885151512631868923798395585286843958863456473305295387128309680 17064
UVM_INFO @ 3720399240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86283061731752964181671394428652109570995465942515950789534473847003744420065 272
UVM_INFO @ 12983967039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24216867621903389202453508029898553961166125584234619201450376973866449653106 98
UVM_INFO @ 137359949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63840105215143119694562120333705247562553418659298768144027502020276033552926 241
UVM_INFO @ 1038112140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30677757299464471129392714207549746588077885171908765515774540307891856983854 98
UVM_INFO @ 63082651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13657987881402588097223379820646981554837472005597968909766786950769210593495 97
UVM_INFO @ 64559652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 106416199664195466651516245346997164962387508751607977466132303282756058808017 97
UVM_INFO @ 506430894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 10 test runs
otp_ctrl_test_access 5171182210208836476445005598617215546960372365000618719384487874228908047197 11350
UVM_INFO @ 750578078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 115762134070368617128702038482951900819316089186301091281962762175257498502920 10444
UVM_INFO @ 13866369963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 46540764697404665709314523393960784223199550579733677821928790805766475657792 3671
UVM_INFO @ 6820520530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_req 111712820167686833846587402230883104965857869922878808930572227305304946097264 4191
UVM_INFO @ 175827489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 32995965820693032880786180056245292834367195062044800564330034200980059492898 34230
UVM_INFO @ 2130410070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 52564010037455099905005065824253173202842643052586196506683191207449230721525 2949
UVM_INFO @ 714465352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 10413779931908219234573797456414679680069334120381271135872320756705183302715 8645
UVM_INFO @ 9970549993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 35197282865633005818494239206845601521044821833448519842299886133850360794142 2491
UVM_INFO @ 4764744228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 90873625151316005083329790691924556036211170281306296991587510792881310330586 3673
UVM_INFO @ 1442981477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 35765039809504848151361934933870074610667561300256043406047246162389272622384 4971
UVM_INFO @ 1407552773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 4 test runs
otp_ctrl_stress_all_with_rand_reset 76012272419302546044767107711969255451665651544035909244127293217182148006535 3314
UVM_INFO @ 1910796981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84925775590242127446783766145580970783164637542757654874626129985392267200016 142
UVM_INFO @ 42177089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102854841541433190511385538534497002275712414233282426157747616349675913823586 6336
UVM_INFO @ 2989006967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42167895206158408930541383613243144843604365178448341633872480317382521519207 254
UVM_INFO @ 693985344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:961) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 3 test runs
otp_ctrl_parallel_lc_req 18950500779895166891120588635280052389038487576039512518252882602029372953521 4525
UVM_INFO @ 590753163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_req 13879693568042105729482574393382291144682823087201342570125495637335683939040 8137
UVM_INFO @ 892773323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 113309723304716200183505250473854014534134662446684769251138760596502650326426 11402
UVM_INFO @ 1726520733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 3 test runs
otp_ctrl_stress_all 13787897810733594832995467366085616061874043591671637239550875188784015267635 8424
UVM_INFO @ 2840549819 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 2840865611 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 2841102455 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 2841128771 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
otp_ctrl_stress_all_with_rand_reset 16392162919174773035186113526800619200236823862014254528137386540708864131613 207
UVM_INFO @ 175127966 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 175372862 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 175597350 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 175842246 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
otp_ctrl_stress_all_with_rand_reset 112869064026523277659309974248742261193929715337017756289849914561153499165093 7651
UVM_INFO @ 21997338281 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 21999171618 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 21999838286 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 22001671623 ps: (otp_ctrl_scoreboard.sv:572) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_ERROR (cip_base_vseq.sv:1296) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
otp_ctrl_stress_all_with_rand_reset 30147042710691288077098815249570243811921374660417529267663299252544445078625 23649
UVM_INFO @ 43602404055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59212011326855012571202860467955389366254050322896616198112507179438190206183 19441
UVM_INFO @ 8263177144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 972721265709440842348815649727792092960744202574549741150158981032350868127 3529
UVM_INFO @ 19536079374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 2 test runs
otp_ctrl_low_freq_read 33515933976103039746342038890486347954116882890794542317414192241988108352937 95
UVM_INFO @ 26642503318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 9661072492771831471723421564928496834982460271125953008975804159469386775632 96
UVM_INFO @ 63763307661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 42378419729794386176374876044506766158107196686475000632616905612844564809618 110319
UVM_INFO @ 7597279334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *a* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 60339402258561379055684062233569828923091660885288732790959751701255230773033 2032
UVM_INFO @ 12352300930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:309) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 92119296870692426195099682815756675677027125492381883175728263366085270454070 432
UVM_INFO @ 8906898906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_dai_errs_vseq] wait timeout occurred! 1 test run
otp_ctrl_dai_errs 37331762191572509875877320118089511586363391103515318217435963101113040718776 94
UVM_INFO @ 10008871322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 1 test run
otp_ctrl_stress_all_with_rand_reset 111655260144206567701835772216536122562452733485333993667063340249612498088592 7242
UVM_ERROR @ 16144058585 ps: (otp_ctrl_if.sv:391) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 16144058585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 37152919159569555437632960843360109598418272074328255147708586524151024712160 4371
UVM_INFO @ 28725578616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_macro_error does not trigger! 1 test run
otp_ctrl_init_fail 45576762979422200711205324553179759783151169890332872999092674657672386220326 2430
UVM_INFO @ 314002332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_stress_all_with_rand_reset 40404695336596306394882305989200852992319415678753627213142048509214644233415 9676
UVM_INFO @ 11041905028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
otp_ctrl_stress_all_with_rand_reset 110342397287215700795070841112746750600429882776429486521825432533992104719798 None
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr a0c rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 5966860404689383462236375205819161038834153924512225183566461337414265929310 2618
UVM_INFO @ 8776312999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1375) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger! 1 test run
otp_ctrl_init_fail 101006713124223067188009240965356634949116867002579390149749461439617475129308 1668
UVM_INFO @ 186858368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---