Simulation Results: rom_ctrl/64kb

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.61 %
  • code
  • 83.86 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 79.06 %
  • line
  • 79.28 %
  • branch
  • 80.93 %
  • toggle
  • 84.74 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
85.92%
V2S
66.10%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.000s 383.368us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.000s 62.559us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 3.000s 94.229us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 99.578us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 58.693us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 59.156us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 3.000s 94.229us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 58.693us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 67.674us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 77.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 3.000s 2.802us 0 2 0.00
stress_all 12 20 60.00
rom_ctrl_stress_all 10801.000s 0.000us 12 20 60.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 9.000s 749.403us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 4.000s 57.492us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 9.000s 167.605us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 9.000s 167.605us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 6.000s 62.559us 1 1 100.00
rom_ctrl_csr_rw 3.000s 94.229us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 58.693us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 65.388us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 6.000s 62.559us 1 1 100.00
rom_ctrl_csr_rw 3.000s 94.229us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 58.693us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 65.388us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.000s 9162.687us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 280.000s 430.766us 5 5 100.00
rom_ctrl_tl_intg_err 60.000s 2858.473us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 280.000s 430.766us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 280.000s 430.766us 5 5 100.00
sec_cm_checker_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_checker_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_checker_fsm_local_esc 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 280.000s 430.766us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 280.000s 430.766us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.000s 383.368us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.000s 383.368us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.000s 383.368us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 60.000s 2858.473us 25 25 100.00
sec_cm_bus_local_esc 2 22 9.09
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
rom_ctrl_kmac_err_chk 9.000s 749.403us 2 2 100.00
sec_cm_mux_mubi 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_mux_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_ctrl_redun 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.000s 9162.687us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 280.000s 430.766us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 20 40.00
rom_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 8 20 40.00

Error Messages

   Test seed line log context
Job timed out after * minutes 36 test runs
rom_ctrl_stress_all 27357901701509715675066003313741579673383640245532095868112049080625728078561 None
rom_ctrl_corrupt_sig_fatal_chk 106243989570263596287038815963098027149051486793752985700720117609895904983044 None
rom_ctrl_stress_all_with_rand_reset 1398180702125987172280196019450946220991655731293238922971441924616434864812 None
rom_ctrl_corrupt_sig_fatal_chk 57013643232372747846425443007989426597821861574821505979094799750846564551459 None
rom_ctrl_corrupt_sig_fatal_chk 98560077324686771268896181398006447052900156930575770699629990023027387189943 None
rom_ctrl_stress_all_with_rand_reset 102765942045687964907755180248526648000342937346755238202876780917930944174589 None
rom_ctrl_stress_all 68440507182172327581934473044220556396528956363467304068615178853850655768003 None
rom_ctrl_corrupt_sig_fatal_chk 68065819540584969918623909039344396058018282666253138118185263251316404889574 None
rom_ctrl_stress_all_with_rand_reset 79831182105336071593279126774045665855222310963339725783813058678794093440109 None
rom_ctrl_corrupt_sig_fatal_chk 42633719360449138714735614233338275529212483794729722255633868960414112351660 None
rom_ctrl_corrupt_sig_fatal_chk 110905661209354276294912436618556714012679309633828504729862950421454420402143 None
rom_ctrl_corrupt_sig_fatal_chk 20062100289207713475331053001214595664597242774445644836553412076190104714732 None
rom_ctrl_stress_all 20041712366371471950062009132505900106797840273568300618168075035354964772842 None
rom_ctrl_corrupt_sig_fatal_chk 69317620606614468549960680419432151228796143131665198834291254742647850674022 None
rom_ctrl_stress_all 111275975218944593784217516979609321966376373452069908492845296546097662294667 None
rom_ctrl_corrupt_sig_fatal_chk 499658319466301320760634753435035481443918860496985537376924778639176202844 None
rom_ctrl_corrupt_sig_fatal_chk 113025604570506142302283135333918447357690537547613738320212219747073942988985 None
rom_ctrl_stress_all_with_rand_reset 5586918794275387769537097316877792645417388667824269925924570122508888139962 None
rom_ctrl_corrupt_sig_fatal_chk 43822818903914940405334889823169172285991338426869961087450860783173579317509 None
rom_ctrl_stress_all_with_rand_reset 5414375075770720204583066304918432192062473046317430518735625047431727421071 None
rom_ctrl_corrupt_sig_fatal_chk 85776930235085565134890242317193056662989384777258651707320606793105202367343 None
rom_ctrl_stress_all 104299931908841121443768744724666424334141171456395038585120687690195538611727 None
rom_ctrl_corrupt_sig_fatal_chk 97377130684211779013938378832797903690171324389228319624055048199210702782265 None
rom_ctrl_stress_all_with_rand_reset 111485613271825041250445581076168547104886875107186524955873803164406791581518 None
rom_ctrl_corrupt_sig_fatal_chk 67992826678368655311528052257273841306494049579711194669783593368860971752049 None
rom_ctrl_corrupt_sig_fatal_chk 95403545318891020492575659312204917920937585518181513840290087441391361459022 None
rom_ctrl_stress_all 74680929461794393362603846918379632385013042079319458508892527750638161303883 None
rom_ctrl_corrupt_sig_fatal_chk 77615567509250443909270208254729147023830552798894701544830491194782100926281 None
rom_ctrl_corrupt_sig_fatal_chk 54928664219218070548784539765379373969533607003770809533900625653662274462781 None
rom_ctrl_stress_all_with_rand_reset 103543777919155146069570907447850154958281837380281207433240074333839839749439 None
rom_ctrl_stress_all 107119031438663732430847100979419009430085085532778872365716308428973771798819 None
rom_ctrl_corrupt_sig_fatal_chk 59953505145781344488975285156682946028331231292041845157724487128765049744034 None
rom_ctrl_stress_all_with_rand_reset 109114180190637067685963216769250890830002288278700390984847969490023684857720 None
rom_ctrl_stress_all 97561326240523311323769769336370971397293052406685443805602910251491066221470 None
rom_ctrl_corrupt_sig_fatal_chk 50706797861868196458818263780910103132801641812848185650558467514044057636435 None
rom_ctrl_corrupt_sig_fatal_chk 36939654304052079716056334685245037504984210881055415469422291191426234492247 None
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 3 test runs
rom_ctrl_stress_all_with_rand_reset 63641657855875891745397103911352414322611794078646427604569581327243755168782 92
UVM_INFO @ 248140090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 57317447361949908420694370213371291359190386348558550690515774758085032709569 95
UVM_INFO @ 535250782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 102913376177808290957609004953547259604306731043993785109737321663287695196019 94
UVM_INFO @ 2577256731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 17568245464318034707230701439231972240800685601900507440425259183476351336860 88
UVM_INFO @ 2802379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 1917367132580954419750580463983095492091412415767805543195911188144920824011 88
UVM_INFO @ 333558703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:354) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 74180870508267810760370164041191724598335182295902088127264428152956062972049 110
UVM_INFO @ 362883684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---