Simulation Results: rstmgr

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.92 %
  • code
  • 99.56 %
  • assert
  • 98.72 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 99.90 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 1.780s 74.418us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.420s 62.736us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.280s 37.717us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.600s 122.971us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.450s 37.499us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.120s 96.970us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.280s 37.717us 5 5 100.00
rstmgr_csr_aliasing 1.450s 37.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 2.240s 171.018us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 1.600s 52.031us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.620s 80.814us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 8.500s 731.869us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 8.500s 731.869us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 8.500s 731.869us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 8.500s 731.869us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 47.940s 4050.516us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.250s 40.000us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 3.420s 89.417us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 3.420s 89.417us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.420s 62.736us 1 1 100.00
rstmgr_csr_rw 1.280s 37.717us 5 5 100.00
rstmgr_csr_aliasing 1.450s 37.499us 1 1 100.00
rstmgr_same_csr_outstanding 1.790s 76.016us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.420s 62.736us 1 1 100.00
rstmgr_csr_rw 1.280s 37.717us 5 5 100.00
rstmgr_csr_aliasing 1.450s 37.499us 1 1 100.00
rstmgr_same_csr_outstanding 1.790s 76.016us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rstmgr_sec_cm 33.280s 4310.227us 5 5 100.00
rstmgr_tl_intg_err 15.140s 1947.301us 25 25 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 33.280s 4310.227us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 33.280s 4310.227us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
rstmgr_tl_intg_err 15.140s 1947.301us 25 25 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.630s 65.511us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 25 25 100.00
rstmgr_leaf_rst_cnsty 6.290s 484.981us 25 25 100.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 3.440s 291.477us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 33.280s 4310.227us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.280s 37.717us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.280s 37.717us 5 5 100.00