Simulation Results

Simulation Results: rv_dm/use_dmi_interface

21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.96 %

code
84.63 %

assert
96.90 %

func
97.34 %

block
93.90 %

line
94.43 %

branch
83.49 %

toggle
80.25 %

FSM
80.36 %

Validation stages

V1		96.92%
V2		43.89%
V2S		94.00%
V3		15.00%
unmapped		0.00%

126/130 passed

96.92 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	50.000s	4833.682us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	51.000s	832.130us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	52.000s	113.083us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	81.000s	19251.288us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	53.000s	838.937us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	56.000s	3774.982us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	70.000s	5871.111us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	102.000s	36358.920us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	257.000s	259650.738us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	52.000s	359.496us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	52.000s	923.581us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	52.000s	349.966us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	49.000s	90.249us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	48.000s	267.621us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	52.000s	1111.661us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	48.000s	194.292us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	50.000s	577.480us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	52.000s	359.496us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	51.000s	401.211us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	52.000s	1098.572us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	52.000s	349.966us	2	2	100.00
rom_read_access				0	2	0.00
	rv_dm_rom_read_access	50.000s	60.473us	0	2	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	40.000s	427.846us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	53.000s	306.235us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	73.000s	18216.567us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	68.000s	2105.445us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	52.000s	216.028us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	68.000s	2105.445us	1	1	100.00
	rv_dm_csr_rw	53.000s	306.235us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	46.000s	71.292us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	43.000s	70.931us	1	1	100.00

79/180 passed

43.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	50.000s	4833.682us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	52.000s	870.996us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	52.000s	779.654us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	47.000s	115.079us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	52.000s	317.478us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	68.000s	6740.269us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	63.000s	127.054us	0	20	0.00
bad_sba				2	20	10.00
	rv_dm_bad_sba_tl_access	74.000s	142.097us	2	20	10.00
sba_autoincrement				4	20	20.00
	rv_dm_autoincr_sba_tl_access	174.000s	45562.519us	4	20	20.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	51.000s	179.608us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	54.000s	4000.335us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	51.000s	820.816us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	51.000s	166.083us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	54.000s	4903.629us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	130.000s	5084.405us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	47.000s	60.536us	1	1	100.00
stress_all				0	20	0.00
	rv_dm_stress_all	10800.000s	0.000us	0	20	0.00
alert_test				10	10	100.00
	rv_dm_alert_test	50.000s	192.745us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	54.000s	803.591us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	54.000s	803.591us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	68.000s	2105.445us	1	1	100.00
	rv_dm_csr_hw_reset	40.000s	427.846us	1	1	100.00
	rv_dm_csr_rw	53.000s	306.235us	5	5	100.00
	rv_dm_same_csr_outstanding	58.000s	2008.366us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	68.000s	2105.445us	1	1	100.00
	rv_dm_csr_hw_reset	40.000s	427.846us	1	1	100.00
	rv_dm_csr_rw	53.000s	306.235us	5	5	100.00
	rv_dm_same_csr_outstanding	58.000s	2008.366us	5	5	100.00

V2S

47/50 passed

94.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	52.000s	649.273us	5	5	100.00
	rv_dm_tl_intg_err	81.000s	3106.159us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	81.000s	3106.159us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	54.000s	4000.335us	2	2	100.00
	rv_dm_debug_disabled	52.000s	115.741us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	54.000s	4000.335us	2	2	100.00
	rv_dm_debug_disabled	52.000s	115.741us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	50.000s	4833.682us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				7	10	70.00
	rv_dm_buffered_enable	53.000s	217.868us	7	10	70.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	51.000s	175.967us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	51.000s	175.967us	4	4	100.00
sec_cm_exec_ctrl_mubi				7	10	70.00
	rv_dm_buffered_enable	53.000s	217.868us	7	10	70.00

3/20 passed

15.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				3	20	15.00
	rv_dm_stress_all_with_rand_reset	84.000s	3075.634us	3	20	15.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	138.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared:				39 test runs
	rv_dm_sba_tl_access	93445678875114022579094770114683631715353302678308352696412322013566558815198	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_sba_tl_access	17007644212233305618069650139440248599979418581507179337520401193074498362150	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23827
	rv_dm_bad_sba_tl_access	9669090395656880575724528902163011836176511511874682836613419608683720996846	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23821
	rv_dm_sba_tl_access	55154240981381733739098850722178319710883392208938228183056252310137140826551	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23792
	rv_dm_sba_tl_access	95971049969249443635769019060468307542880440306808145039555466753963999846655	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23828
	rv_dm_autoincr_sba_tl_access	85990209831062339814816283125393459150609077603094855867861486368828342182372	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24278
	rv_dm_sba_tl_access	24709006101785428866652690246115718655420672416032711013064412236629906666602	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23803
	rv_dm_bad_sba_tl_access	8710839839791660113733238571882362695987626563001625717922544380885828868202	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23903
	rv_dm_autoincr_sba_tl_access	14980126200640937181875047711604141037604489144462340081255304627922532173075	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23755
	rv_dm_sba_tl_access	53044837960182894377429935458557422147315058550485178212222197343499545756616	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23853
	rv_dm_autoincr_sba_tl_access	14383022741966486798670985179463867599225035736946704032737142163386906773908	135	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24081
	rv_dm_sba_tl_access	60950864622028856459499305027188742768254792211237477454508496283914936285025	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_bad_sba_tl_access	92106260061922180436575525539811932830803596026745283569962099748437462041046	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23950
	rv_dm_autoincr_sba_tl_access	43135976548233579622619749000726518646434130654617098333969540524519159359515	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23874
	rv_dm_sba_tl_access	19019252027400451417619165120850299634846207474110546322529466784543332472310	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23807
	rv_dm_bad_sba_tl_access	22729457671906183807158847222904975932555696963690068290196125139830015991137	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23933
	rv_dm_autoincr_sba_tl_access	12171837281944128373090558197062091825052559902327884400418891502549061752216	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23956
	rv_dm_sba_tl_access	113953941343473347164247529942800828790972246286162727990312669056365313274777	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23921
	rv_dm_sba_tl_access	26883945906134847255756549403640529938532220381642073032285736042333652420595	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_bad_sba_tl_access	58956280621694267628853436350336973375472403432152532810371216613358974190651	135	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23822
	rv_dm_sba_tl_access	102980627832649805625879177270446010068813475867331729700061100595985119487378	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23808
	rv_dm_bad_sba_tl_access	2055494099839253695551626090055441270551868666070696041349374933398523876660	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23890
	rv_dm_sba_tl_access	4398026020682436516931692093630278387276371510266176411947787971311979163146	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23817
	rv_dm_autoincr_sba_tl_access	33876169965230093148653846390949869200682197644908164309773961613207836633521	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23737
	rv_dm_sba_tl_access	64918496986569662424522021463050535103448666534592373863207702665969567804445	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_autoincr_sba_tl_access	18241409335465425907761721167483561492148730480754527379866853935562965784314	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23944
	rv_dm_sba_tl_access	66873831776330622567595246331098677138703280445502463116922227138385385389840	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23803
	rv_dm_sba_tl_access	81052056219647888846512814559240747823133328078679528872610606767097611384409	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23807
	rv_dm_autoincr_sba_tl_access	63494516346550309228000454099962624937750009856956190396300021096646310065652	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23782
	rv_dm_sba_tl_access	12650494149533309123456508999951892815559007178077159064993953812512220019926	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23821
	rv_dm_bad_sba_tl_access	1739810226422034561697862114643632035683240040349298567431518311903355519266	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24081
	rv_dm_sba_tl_access	75892430183865174970559666556964287355453997927480816935481456040277892196779	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23854
	rv_dm_sba_tl_access	3466809515837558494398036585990917959256248090317125569375016808545110698736	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23886
	rv_dm_bad_sba_tl_access	70145806221914823891720360134415402414473616250429127674149630462547791906991	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23822
	rv_dm_sba_tl_access	19049017782165686778317508258361818555667104408272381046843086319786661550391	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23823
	rv_dm_bad_sba_tl_access	6687309342720417341528791002945498080061969953971180400445581689737241983605	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23882
	rv_dm_autoincr_sba_tl_access	26565449459213802378198608636692662925093554226577449462797185880891619759396	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23874
	rv_dm_sba_tl_access	74776929662673750014416261069801423403692334399731613854943631425113450382045	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23808
	rv_dm_autoincr_sba_tl_access	43655057354096070366745898354522320759849732876626543933020584166408219609997	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23973
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				35 test runs
	rv_dm_delayed_resp_sba_tl_access	26896850508091601854376754303538822815192102970010245222022707120310591255972	107	UVM_INFO @ 91734689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	107398059655684020907825376016612746271118189051018266499001983814098666777106	107	UVM_INFO @ 154572089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	109404371644240873715944799399597655553028096148118158844820677347786799329757	107	UVM_INFO @ 1365515110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	31518062811994093454652447623200709456152735816554092721612902838683356580576	107	UVM_INFO @ 72260675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	6823554983625516873301829613789606099825717414890132077582266921378212226165	107	UVM_INFO @ 81120593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	26477737431004405547864877736355964767452911316470124439009884652079198474988	107	UVM_INFO @ 141933505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	24623862180121402013909683674317546736384288786346791948259797938748899799431	107	UVM_INFO @ 94855056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	13493427046753109173395819656350706115832474509456075195963411871755828155625	107	UVM_INFO @ 255815990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	80770311487814851834268813648053989520708157520973674950680644536455570119656	107	UVM_INFO @ 237270383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	84521542003422571083985814186697157252492472442954576658000534218028287497494	107	UVM_INFO @ 86735986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	18571671499633209420241265527087727289812417959215714393248253311660050012104	107	UVM_INFO @ 171368781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	76274533346270920841473608489378740354492685642321271344135667933060755346856	107	UVM_INFO @ 144732715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	17075681969743865055853734962328595948091552087504376986373559530262880452741	107	UVM_INFO @ 406362171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	113658196948121533426632957437302250353710574780228166845613520758524141293656	107	UVM_INFO @ 127379773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	1899218922541817283658708231163661918686819959586309642569912343084825406915	107	UVM_INFO @ 219590561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	76079027212019995800476900816819697600453578087957043628757092900277581146961	107	UVM_INFO @ 69713399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	114883935079244543122007946583795195849369677037866401150479201544710175867213	107	UVM_INFO @ 286550695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	98014053151099487669291466876692891079898672179554374142705155159753747153530	107	UVM_INFO @ 127054255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	51570863574382335397188261333074463220761073251734838129896214674018619174655	107	UVM_INFO @ 142097485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	27551783822064879509769149919344425596713648441509663404545037683689394005471	107	UVM_INFO @ 212272601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	7250947514794251972486120510056254219573080850078743200230564159438782198623	107	UVM_INFO @ 206653938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	106206581573898570218673332800103280847488175532664241198946166023474823917533	107	UVM_INFO @ 105981934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	87892496484642147413079132676913376643255422639015499970729475044350935173607	107	UVM_INFO @ 1032538052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	5837428063341789658058585369247384231810950307321318011635102454852125164277	107	UVM_INFO @ 123281071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	34167835500871666198153007516085359991500525018915862661952428976766707427990	107	UVM_INFO @ 325595431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	40358088003166620550457890122008654665684923481184135696494087998569790846083	107	UVM_INFO @ 184177224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	53423159589448468433952336074824476295708026800769587139355954232710722676056	107	UVM_INFO @ 85917380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	63181477814712587342360687005102271598963914260386062634595820363980314143263	107	UVM_INFO @ 462821156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	65659051569117888447624334790025399502930431578493543251838669682991080727024	113	UVM_INFO @ 2606475758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	57298568070781595336333812250959201906719545583935889171871832874817265770111	107	UVM_INFO @ 102166456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	104106119345490422426789412104495745532157783136916051236633023812607683861833	107	UVM_INFO @ 457702131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	15786287205113567926339459575841289968997773275053565653492627132670163982537	107	UVM_INFO @ 248525967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	114824569939175810277516825153195017526243278895271326684390694649759765729320	107	UVM_INFO @ 430229532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	63064874435355662853749750729280311985622119329286265918487770553590321848166	107	UVM_INFO @ 150506264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	51063209630893249134104392946209463964577519742246550828960132048190483393419	107	UVM_INFO @ 8460477584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				17 test runs
	rv_dm_hart_unavail	3571755472605493077520081521599688768460502872221171919309801805916668756883	87	UVM_INFO @ 39971408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	108683336990556872252075858510675283736945426831135607133836818016583013283513	88	UVM_INFO @ 321697075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	35651480799672278438596960291346021513739808190097493670488341090446414542589	87	UVM_INFO @ 166082954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	10960222689554692887723123038839217006301860800178902519794267113106534925493	93	UVM_INFO @ 2125076690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	45062594530053314063800590531468985033126372268009934653564527559366287369577	87	UVM_INFO @ 79745518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	91064906317487690529000013410227087195517187572660917348527708321932097746289	87	UVM_INFO @ 108072291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	106658663070149991330857056872478374988146346173535834136572742515452564102387	87	UVM_INFO @ 106178196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	49663371130176212759184005791803585320511839039661161109650590931498260751313	100	UVM_INFO @ 944867055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	95866951600362189969627487595027511061885534684442907005832971454029616454274	99	UVM_INFO @ 282424901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	67952337448634072926896728336773181577405624750315247950022226822428991339052	103	UVM_INFO @ 1258541980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	55920041427901657093693526994059812596329390838133466272126210913533178918237	89	UVM_INFO @ 960387568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	26405014568833978764992503031395331750166059193938235955445506836407276796930	92	UVM_INFO @ 445446754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	58960883820351804937827742034538067443738636313735395268720105475155184429359	88	UVM_INFO @ 104971172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	104093275681931439593276953818094929662988891111384043078475680488609477661219	105	UVM_INFO @ 304179881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	78407210518738630225882554502668560594513331714244171085968261261325639200451	110	UVM_INFO @ 3065857025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	58427278273716026635216429465279136146257413264834907315431671244307638350105	157	UVM_INFO @ 3075633880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	40952967014389468286888530327755254953222109538161805711768172898155674655357	88	UVM_INFO @ 216351707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				15 test runs
	rv_dm_mem_tl_access_resuming	111623490699435316384090139250410666327743645926432589682843963588835047527151	87	UVM_INFO @ 90249491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	36061103504232328735976136512409635372071823688271198980919207007794295264005	87	UVM_INFO @ 103177014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	12084986017611044580281644306507541333026738372206514633939874412909652102319	90	UVM_INFO @ 581242013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	88985039792918772367485948695134208731460740800308053826516230823729235585147	93	UVM_INFO @ 5450408658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	87244186713602012230622096729521107502763157051709566078809237431438897992071	120	UVM_INFO @ 569606148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	15137980331352271496540410277963897616854175309181449378618580368730735343994	88	UVM_INFO @ 300143012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	6510201520694403018260344868900640430332340614307635701766773630776149421660	102	UVM_INFO @ 835343818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	96658742135116566712712306653961163589852226452694275050502793615575629817644	89	UVM_INFO @ 572410757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	36297855948861293944348986266056665075335557273768783013709090077798907926870	89	UVM_INFO @ 630968635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	14797740342610858668034221652499183938051099097484806772354795310318540728945	112	UVM_INFO @ 553429483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	85293995982412759940928257484323665864330853360262537832799860417727962789751	88	UVM_INFO @ 139701509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	37070192273152661211817978627885503314997424357101679662073812442449868459923	93	UVM_INFO @ 369935794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	65456908129030937672031256234198272527750513810618270756943652159315099307351	91	UVM_INFO @ 115872463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	75505551126636658904032686281935657326027496402594405804233564269378342737290	107	UVM_INFO @ 1149896613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	74636091027135925085656125318611070572692951669349889959851042087254302283354	89	UVM_INFO @ 373465949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				9 test runs
	rv_dm_jtag_dmi_debug_disabled	34493180208754176941228327657880818051681224138091093629383570966469703111407	87	UVM_INFO @ 81998852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	95948831794208380941408997184722553894594192669509465670501481710271025522414	87	UVM_INFO @ 179608265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	100488967411252282101438563392355400938267633443262271385877786195649915932781	91	UVM_INFO @ 2792806376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	31674584104011828772283846112409308892776185126110665023126195067029828294831	88	UVM_INFO @ 341697166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	675881261964751901485918442413862936845328410914260416278201730479024538593	88	UVM_INFO @ 646141051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	29394453114803527361991883987463387595481865113476152003870435959514533198055	97	UVM_INFO @ 500925209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	75675484942103399058499850997057198060617020768432392296122494640113538110835	105	UVM_INFO @ 574418709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	86636285117323727527123774262118913523624320536562787857096130972216577843330	90	UVM_INFO @ 516106860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	5535276863542621912513859122038378975994088416529625853076056357686637890028	95	UVM_INFO @ 490824566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				3 test runs
	rv_dm_scanmode	78968956601870110960166009544960680227220263946898706265180615488962442612319	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	99210738467473345736483361877373512919388813957423887194738111782241919356403	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	4119318645685387265702208287737448621234600487796700794089097054646765623016	91	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				3 test runs
	rv_dm_buffered_enable	34844589992433524924138035250983007721296788919500843112661437351048046366144	93	UVM_INFO @ 378177195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	92218726852761543822968221252337059573486193986579974875897111179394520995243	92	UVM_INFO @ 501397604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	16979122861265081654871057692622176654364217293294747282085574700110481760287	89	UVM_INFO @ 118685239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [rv_dm_common_vseq] Check failed (vseq_done)				2 test runs
	rv_dm_stress_all_with_rand_reset	60358622113826480267475817161552826017361212535726480136131826240077593465903	126	UVM_INFO @ 2523647759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	38183538523055649442375659790143538036006559096930084395448007595172990532655	95	UVM_INFO @ 1496378035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23864) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	8783343514839046138983833477737064717001027033177583862010655633093765884199	87	). UVM_INFO @ 60472600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23859) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	31438165311956111512349823637650068852870126586730722745152463274742097518907	87	). UVM_INFO @ 88331214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	rv_dm_stress_all	113200047344019855224913709527716977044390305423833851100118154292733754909343	None