Simulation Results: rv_timer

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
55.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 668.127us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 52.450us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 2.000s 16.743us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 630.894us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 57.543us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 201.343us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 2.000s 16.743us 5 5 100.00
rv_timer_csr_aliasing 1.000s 57.543us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 20 20 100.00
rv_timer_random_reset 15.000s 36434.167us 20 20 100.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 2257.600us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 235.000s 313448.739us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 235.000s 313448.739us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 7.000s 4333.266us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 1.000s 11.937us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 1.000s 35.753us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 4.000s 200.405us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 4.000s 200.405us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 52.450us 1 1 100.00
rv_timer_csr_rw 2.000s 16.743us 5 5 100.00
rv_timer_csr_aliasing 1.000s 57.543us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 51.848us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 52.450us 1 1 100.00
rv_timer_csr_rw 2.000s 16.743us 5 5 100.00
rv_timer_csr_aliasing 1.000s 57.543us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 51.848us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 2.000s 246.196us 5 5 100.00
rv_timer_tl_intg_err 2.000s 93.657us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 93.657us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 3.000s 1834.124us 2 10 20.00
max_value 0 10 0.00
rv_timer_max 6.000s 165.573us 0 10 0.00
stress_all_with_rand_reset 20 20 100.00
rv_timer_stress_all_with_rand_reset 60.000s 6271.235us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 24432673330040738958372614392679526993553261673259744435775165199658185947445 85
UVM_INFO @ 89602063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 63662570536321117333332448718296127076171674946074192977517360489288044849672 84
UVM_INFO @ 711739592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 77964508175737654905798192459333086046394815316214074228731299924137098746445 84
UVM_INFO @ 165573292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 47171026576833494599204038178322788160696825407022572900503328516374229888611 84
UVM_INFO @ 170291060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 114661169206022296331128681332743910633099983170189169757166898895968912223476 84
UVM_INFO @ 144860327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 97273759477472733108891759824752846810906354063041496016709470087277351527139 84
UVM_INFO @ 86150212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 61259422049810257657785303952945141901021898935159475632005473017349572931543 84
UVM_INFO @ 89229525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 65012902025338687673380367616220957418056625283744080784428809873562674502411 84
UVM_INFO @ 44489411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 5125279823470794997388395754763346576879746314365509299732132733110256365688 84
UVM_INFO @ 133072532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 8 test runs
rv_timer_min 58737543911507654313785944158883832998777655341019819156604744068318195144343 86
UVM_INFO @ 263225054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 10538902370313862796048476572993047366771963986551681902407383514219765448004 88
UVM_INFO @ 89566430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 51993375763448616451340739799336318726415436249818021705813931152875340058056 86
UVM_INFO @ 75637477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 65556196145281239848841488466750190700697366694895246367456384942787547688899 84
UVM_INFO @ 130519293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 70436766357102318804432539429571332730524018313652624176321736296189671864302 87
UVM_INFO @ 69780413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 75524164837221516851844418782014131848230404970540705342867955698231383085831 85
UVM_INFO @ 70073887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 40790934548185074353311642936624584231058815143326421826613396227561126499919 86
UVM_INFO @ 72738958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 20703458942496527468488118030034316152098187878521486417939878033060119288199 85
UVM_INFO @ 1834124198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:343) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 106271677431458371740579113036965381572276944039719356119745683318371791089615 84
UVM_INFO @ 530988529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---