Simulation Results: spi_host

 
21/08/2026 15:00:36 DVSim: v1.49.0 sha: ffb3622 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.19 %
  • code
  • 95.03 %
  • assert
  • 96.79 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 62.000s 3060.298us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 88.395us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 21.597us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 286.400us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 53.308us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 73.853us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 21.597us 5 5 100.00
spi_host_csr_aliasing 2.000s 53.308us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 15.973us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 26.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 25.362us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 16.000s 1115.311us 10 10 100.00
spi_host_error_cmd 2.000s 20.935us 10 10 100.00
spi_host_event 37.000s 2066.063us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 12.000s 582.637us 10 10 100.00
speed 10 10 100.00
spi_host_speed 12.000s 582.637us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 12.000s 582.637us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 351.000s 46303.608us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 70.000s 3647.089us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 91.739us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 12.000s 582.637us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 12.000s 582.637us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 62.000s 3060.298us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 62.000s 3060.298us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 105.000s 2753.248us 10 10 100.00
spien 10 10 100.00
spi_host_spien 45.000s 3140.106us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 110.000s 7664.947us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 4.000s 1060.099us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 16.000s 1115.311us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 53.371us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 17.993us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 131.138us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 131.138us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 88.395us 1 1 100.00
spi_host_csr_rw 2.000s 21.597us 5 5 100.00
spi_host_csr_aliasing 2.000s 53.308us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 129.107us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 88.395us 1 1 100.00
spi_host_csr_rw 2.000s 21.597us 5 5 100.00
spi_host_csr_aliasing 2.000s 53.308us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 129.107us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 7.000s 57.625us 25 25 100.00
spi_host_sec_cm 2.000s 182.367us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 7.000s 57.625us 25 25 100.00