| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2690.041us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 5.000s | 15.443us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 5.000s | 42.475us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 7.000s | 459.091us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 6.000s | 57.479us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 8.000s | 371.839us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 5.000s | 42.475us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 6.000s | 57.479us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 328.000s | 23185.648us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 167.000s | 5278.541us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 67.000s | 41918.150us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 276.000s | 12237.223us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 306.000s | 168164.760us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 92.000s | 27031.822us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 161.000s | 211764.550us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 64.000s | 18350.286us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 6.000s | 690.574us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 501.000s | 207949.778us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 10.000s | 13284.161us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 9.000s | 9544.997us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 7.000s | 1920.275us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 19.000s | 1859.822us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 6.000s | 4779.162us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 460.000s | 37756.527us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 6.000s | 44.721us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 7.000s | 767.104us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 7.000s | 767.104us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 5.000s | 15.443us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 5.000s | 42.475us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 6.000s | 57.479us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 53.255us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 5.000s | 15.443us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 5.000s | 42.475us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 6.000s | 57.479us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 53.255us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 35.000s | 25238.045us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 665.941us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 1481.613us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 665.941us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 1481.613us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 19.000s | 1859.822us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 19.000s | 1859.822us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 5.000s | 42.475us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 64.000s | 18350.286us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 64.000s | 18350.286us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 64.000s | 18350.286us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 161.000s | 211764.550us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3602.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 35.000s | 25238.045us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2690.041us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2690.041us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 64.000s | 18350.286us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 665.941us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 161.000s | 211764.550us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 665.941us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 665.941us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2690.041us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 665.941us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 58.000s | 1918.055us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 73103808257034262430818015702743482005816947815364231938760807361361955751164 | None | ||
| sram_ctrl_mubi_enc_err | 100781911967036615527298021154390057710802798228066119990209932589309884098701 | None | ||
| sram_ctrl_readback_err | 61628254377822091034319235314963572509557291600903228249790072427886201769056 | None | ||
| sram_ctrl_mubi_enc_err | 54374831409037325613909876074936107183076170036953383479675946463329208608679 | None | ||
| sram_ctrl_readback_err | 88494415041302435262517164482257957522057995676191894428377464262198962679219 | None | ||
| sram_ctrl_mubi_enc_err | 15727359684004689670555480281262347137371680848837491152749690476388763024449 | None | ||
| sram_ctrl_readback_err | 4982506803410165232797026270128337220036303092682443311241721369814640527635 | None | ||
| sram_ctrl_mubi_enc_err | 35083943589513137175568952972247702524269170941910082139488905798465452316351 | None | ||
| sram_ctrl_readback_err | 17604788998591908249824966456078028065893121510328508299376622430010814117386 | None | ||
| sram_ctrl_mubi_enc_err | 91963442382195197507874140160150307697390898662350906530666438261376843679676 | None | ||
| sram_ctrl_readback_err | 48234863495693143659921402643173046759380609428945869387036152390416448413355 | None | ||
| sram_ctrl_mubi_enc_err | 68911637587137059537194293834593270918767212827988660101974361487374153106877 | None | ||
| sram_ctrl_readback_err | 46425442543665603665619071789458770128137003395343653245299023607742572690581 | None | ||
| sram_ctrl_mubi_enc_err | 77936555968504785101950443972643443951776016443017861855138365426723478623032 | None | ||
| sram_ctrl_readback_err | 92540625435925064861088116298961771002461580530518675798737521969061840589355 | None | ||
| sram_ctrl_mubi_enc_err | 84476958014799603540583065818485205452209430253576900464720637899467812103320 | None | ||