| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 63.894us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 133.955us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 23.326us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 3.000s | 102.734us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 2.000s | 21.203us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 3.000s | 63.616us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 23.326us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 21.203us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 15.000s | 2255.747us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 7.000s | 1859.025us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 13.000s | 795.482us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 260.000s | 8592.367us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 13.000s | 3234.122us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 26.000s | 1456.137us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 11.000s | 2707.166us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 19.000s | 8847.336us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 3.000s | 68.987us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 267.000s | 120361.415us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 3.000s | 63.836us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 2.000s | 81.974us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 2.000s | 287.403us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 16.000s | 1034.851us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 32.166us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 59.000s | 3870.931us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 26.840us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 609.128us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 609.128us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 133.955us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 23.326us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 21.203us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 82.577us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 133.955us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 23.326us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 21.203us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 82.577us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 2496.852us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 642.028us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 756.902us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 642.028us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 756.902us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 16.000s | 1034.851us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 16.000s | 1034.851us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 23.326us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 19.000s | 8847.336us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 19.000s | 8847.336us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 19.000s | 8847.336us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 11.000s | 2707.166us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 2496.852us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 63.894us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 63.894us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 19.000s | 8847.336us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 642.028us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 11.000s | 2707.166us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 642.028us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 642.028us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 63.894us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 642.028us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 75.000s | 1765.924us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 13579943485817087867888819260246168573490338927834656558595927804455708839361 | None | ||
| sram_ctrl_mubi_enc_err | 25976992780810447866559235793760367392404412597932184584168647231082062011073 | None | ||
| sram_ctrl_readback_err | 61346223261606253197100099491189957302988306792381607020310981526075035368361 | None | ||
| sram_ctrl_mubi_enc_err | 81714776541922744098958646904951007410934062952800949734032323863558383602141 | None | ||
| sram_ctrl_readback_err | 24907999579975214524149172291287251713648153822780319014708456142409341878185 | None | ||
| sram_ctrl_mubi_enc_err | 44231498322169513300954622896333298047145607685485523971115782370190474172312 | None | ||
| sram_ctrl_readback_err | 22001375784307216506002882868712339051762293624785037827449254846482760061045 | None | ||
| sram_ctrl_mubi_enc_err | 88681659612939480176053515873292889273824922665508861861829686845317421531413 | None | ||
| sram_ctrl_readback_err | 12390553217215716985982739970067992567961226300422495939081839078264142898862 | None | ||
| sram_ctrl_mubi_enc_err | 54399460044283812515319320003222638048054643674964523654373708637191371164517 | None | ||
| sram_ctrl_readback_err | 49474462849261348268049738697192735025429813126144123746151704353829764461860 | None | ||
| sram_ctrl_mubi_enc_err | 103257116454843023364060190202765943607304494836861025671921959612342222625588 | None | ||
| sram_ctrl_readback_err | 80582136980818284285547404221596078814589314974256142809293486058798404907703 | None | ||
| sram_ctrl_mubi_enc_err | 100143513969028009380029822255606986727293958342330003178965670637727233229603 | None | ||
| sram_ctrl_readback_err | 46960565290764324607763961258689631999044648923341342016284185940467389792435 | None | ||
| sram_ctrl_mubi_enc_err | 102314937849930932032232788110343796467982525725928055103231026003019239253468 | None | ||